High voltage CMOS logic using low voltage CMOS process

Details High voltage CMOS logic using low voltage CMOS process High voltage CMOS logic using low voltage CMOS process

1994-04-08

1995-11-07

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 81, 326121, 326 24, H03K 1710

Patent

active

054650542

ABSTRACT:
CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors before the gate terminals of each input switching transistor. Each shielding transistor has a gate terminal coupled to a shield voltage of a magnitude substantially midway between ground potential and the positive power supply voltage. The input signal is conveyed by the source-drain channel of the input shielding transistor to the gate of the switching transistor, while preventing the gate of the switching transistor from rising above the shield voltage, in the case of n-channel devices, or below the shield voltage, in the case of p-channel devices. The source-drain channel of a p-channel output shielding transistor couples the output port of p-channel switching transistors to the gate output; the gate terminal of the such p-channel output shielding transistor is coupled to the shield voltage for preventing the drain of p-channel switching transistors from being pulled down below the shield voltage. A similar n-channel output shielding transistor couples the output port of n-channel switching transistors to the gate output for preventing the drain of n-channel switching transistors from being pulled above the shield voltage.

REFERENCES:
patent: 4575721 (1986-03-01), DelGrange et al.
patent: 4636784 (1987-01-01), DelGrange et al.
patent: 4689504 (1987-08-01), Raghunathan et al.
patent: 4704547 (1987-11-01), Kirsch
patent: 4740713 (1988-04-01), Sakurai
patent: 4955696 (1990-09-01), Taniguchi et al.
patent: 4956569 (1990-09-01), Olivio
patent: 5057715 (1991-10-01), Larsen
patent: 5120991 (1992-06-01), Takahashi
patent: 5170155 (1992-12-01), Plus et al.

Affiliated with

Also associated with

Rating

High voltage CMOS logic using low voltage CMOS process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High voltage CMOS logic using low voltage CMOS process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High voltage CMOS logic using low voltage CMOS process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-199193