High throughput die-to-wafer bonding using pre-alignment

Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates

Reexamination Certificate

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Details

C438S015000, C257SE21705, C257SE21480

Reexamination Certificate

active

07897481

ABSTRACT:
A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.

REFERENCES:
patent: 6946322 (2005-09-01), Brewer

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