High threshold PMOS transistor in a surface-channel process

Details High threshold PMOS transistor in a surface-channel process High threshold PMOS transistor in a surface-channel process

2000-05-31

2002-09-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S282000

Reexamination Certificate

active

06448121

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to integrated circuits, and more particularly to a high threshold PMOS transistor utilizing a surface-channel process.
BACKGROUND OF THE INVENTION
In certain integrated circuit designs, a PMOS transistor with high V
t
is required to guarantee a zero through-current in normal circuit operation. This has been accomplished by the use of a “natural” V
t
buried channel PMOS device. However most present day CMOS technology uses surface-channel PMOS transistors, therefore an alternative method is required.
For traditional “buried-channel” PMOS devices, the high V
t
is easy to make. When the PMOS gate material is N+-doped polysilicon, a boron V
t
adjust implant is usually required to reduce the V
t
to the desired voltage, the “natural” V
t
(without V
t
-adjustment implant) is too high for optimum circuit performance. For a buried-channel PMOS process, the V
t
-adjust implant may be blocked from those transistors that need the high V
t
, and both high and low V
t
devices are produced simultaneously. If the natural PMOS V
t
is too high, an extra mask and implant will produce a device with the correct V
t
. For surface-channel PMOS devices, obtaining high V
t
is more difficult. For these devices, the PMOS gate is P+ doped, so the “natural” device has a very low V
t
.
SUMMARY OF THE INVENTION
The invention provides a method for building high V
t
PMOS devices in an otherwise surface-channel process without adding any process steps. A buried-channel PMOS device is fabricated simultaneously with a surface-channel device if the gate is doped N-type while the NMOS gates are doped and the P+ source/drain doping is blocked from the “high” P-channel device. In the normal process the “high” PMOS is not fully self-aligned. However, when the PMOS process includes a lightly-doped drain (PLDD), the LDD doping is self-aligned.


REFERENCES:
patent: 4943537 (1990-07-01), Harrington, III
patent: 5122474 (1992-06-01), Harrington, III
patent: 5580804 (1996-12-01), Joh
patent: 5682051 (1997-10-01), Harrington, III

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