High speed synchronous logic data latch apparatus

Details High speed synchronous logic data latch apparatus High speed synchronous logic data latch apparatus

1995-06-27

1997-07-15

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365194, 365233, G11C 700

Patent

active

056489315

ABSTRACT:
In a logic data latch apparatus including a clock signal input circuit for receiving a clock signal and at least two logic signal input circuits for receiving logic signals, a logic circuit is connected to the logic signal input circuits so that a logic operation is performed upon the logic signals. An output signal of the logic circuit is latched in a latch circuit in synchronization with the clock signal.

REFERENCES:
patent: 3783254 (1974-01-01), Eichelberger
patent: 5295115 (1994-03-01), Furuya
patent: 5426606 (1995-06-01), Takai
patent: 5444667 (1995-08-01), Obara

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