High speed sensing amplifier for an MRAM cell

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S158000, C365S189070, C365S210130

Reexamination Certificate

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11379854

ABSTRACT:
A method and circuits are disclosed for sensing an output of a memory cell having high and low resistance states. A high reference cell is in high resistance state and a low reference cell is in low resistance state. The resistance of the high reference cell in high resistance state has a first margin of difference from the resistance of the memory cell in high resistance state. The resistance of the low reference cell in low resistance state has a second margin of difference from the resistance of the memory cell in low resistance state. Differential amplifiers coupled to the memory cell and the high and low reference cells provide a digital output representing the resistance state of the memory cell.

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H.S. Jeong, G.T. Jeong, G.H. Koh, et al., Fully Integrated 64Kb MRAM with Novel Reference Cell Scheme, Advanced Technology Development and Process Development Team, Samsung Advanced Institute of Technology, IEEE 2002.
Peter K. Naji, Mark Durlam, Saied Tehrani, John Calder and Mark F. DeHerrera, A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM, International Solid-State Circuits Conference, IEEE 2001.

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