Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-12
2002-04-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S795000
Reexamination Certificate
active
06380044
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor processing, and more particularly relates to high-speed semiconductor transistors and a process for forming same.
2. Description of the Related Art
Improvements in semiconductor technology and semiconductor manufacturing are the main drivers to the reduction of cost and the increase in speed of computers. There have been many improvements to semiconductor devices to increase their speed and performance, ranging from packaging of integrated circuits (“chips”) to the wiring of the devices on the chip, to the design of the devices themselves.
Improvements in chip performance are generally obtained by changing the physical structure of the devices comprising the chip by inventing a new process (or improving an existing process) for making the devices. For example, with the continuing need for smaller integration densities and faster operational speeds, dopant impurity profiles for integrated devices are becoming increasingly shallower with greater dopant concentrations, as compared to previous generations of integrated devices. The shallower dopant profiles and greater dopant concentrations are used to decrease the sheet resistance of-the source and drain regions to obtain faster transient response or logic-state switching rates relative to previous chips.
Thermal annealing techniques, such as rapid thermal annealing (RTA) or rapid thermal process (RTP), are becoming less attractive as options for performing activation annealing of doped regions of an integrated device after dopant implantation. This is mainly because thermal annealing techniques typically require heating the entire substrate to a maximum temperature for a time sufficient to activate the integrated device's source and drain regions, after which the substrate is permitted to cool to quench the doped source and drain regions. This approach is problematic because the substrate is capable of holding a relatively large amount of thermal energy, which requires significant time to be dissipated via radiation and convection before the dopant ions become incapable of moving due to solidification of the doped regions. Therefore, during the time required for the substrate to cool, the dopant ions can readily move beyond the intended boundaries of the doped regions (a phenomenon which is sometimes referred to as “transient enhanced diffusion”). As a result, the junction depth of the source/drain regions becomes greater than desired. This, in turn, leads to increased off-state leakage currents and thus reduced device performance.
The speed of semiconductor devices has also been limited to date by physical constraints on the amount of activated dopant concentrations. More specifically, for any two species of dopant and substrate ions, under equilibrium conditions, there are only a certain number of dopant ions that can be positioned at activated sites within the crystalline lattice of substrate ions. This limit is known as the ‘solid solubility limit’. It is generally not possible in the fabrication of semiconductor devices to attain activated dopant concentrations above the solid solubility limit. With thermal annealing techniques, the minimum sheet resistance attainable in the doped regions is controlled by the solid solubility limit, which is 3×10
20
ions/cm
3
for boron, 2×10
21
ions/cm
3
for arsenic, and 1.5×10
21
ions/cm
3
for phosphorous. Lower sheet resistance in the doped regions of an integrated device generally leads to faster transient response or logic-state switching rates. Accordingly, it would be desirable to increase the dopant concentration in active sites within an integrated device's doped region(s) to levels above the solid solubility limit. Such dopant concentrations are not presently attainable with known conventional annealing techniques.
The nature of the dopant profiles and the carrier concentration affect the performance of the chip. A gradual dopant profile is prone to higher spreading resistance, while a reduced carrier (dopant) concentration can result in a higher sheet resistance than is desired. The formation of abrupt junctions (e.g., sharp dopant profiles) reduces overlap capacitance and spreading resistance, and the ability to increase the dopant concentration lowers the sheet resistance. Both these effects serve to increase the speed and improve the performance of the chip.
There are many prior art semiconductor processes pertaining to improving the performance of a semiconductor device by changing the properties of the device. For example, U.S. Pat. No. 5,756,369 (the '369 patent), entitled “Rapid thermal processing using narrowband infrared source and feedback”, describes rapid thermal processing (RTP) of a semiconductor wafer performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer. However, a shortcoming of this technique is that the temperature of the entire wafer rises to the dopant activation temperature (typically from 800° C. to 1100° C.). Also, a silicon film is required to be deposited on the backside of the wafer. In addition, a continuous wave CO
2
laser is used, which does not allow for sufficient cooling of the wafer region being processed for many applications.
U.S. Pat. No. 5,897,381, (the '381 patent) entitled “Process of forming a layer and semiconductor substrate”, discloses and claims a process of forming a layer on a semiconductor substrate having a front side and a backside, the process comprising the steps of placing a film of material in contact with the backside of the substrate, then directing a beam of narrowband energy onto the film such that the film absorbs the energy and transfers heat to the substrate, then controlling temperatures across the backside of the substrate, and then finally performing an additive process on the front side of the substrate. However, like the '369 patent, the '381 patent has the shortcoming that the entire wafer rises to the dopant activation temperature (typically from 800 to 1100° C.) when heated. Also, a silicon dioxide film needs to be deposited at the back of the wafer, and a continuous wave CO
2
laser is used, which does not allow for sufficient cooling of the wafer region being processed for many applications.
U.S. Pat. No. 5,908,307, entitled “Fabrication process for reduced-dimension FET devices”, describes pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth which provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology. However, a shortcoming of this technique is that the polygate may not be able to stand the high laser fluence without appreciable deformation. Another shortcoming is that undesired silicon melting underneath the trench isolation is likely to occur.
U.S. Pat. No. 4,617,066, entitled, “Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing”, describes a process for producing hyperabrupt P± or N± regions in a near-surface layer of a substantially defect free crystal, using solid phase epitaxy and transient annealing. The process for producing a hyperabrupt retrograde distribution of the dopant species begins with amorphizing the near-surface layer of a base crystal, and then implanting a steep ret
Talwar Somit
Thompson Michael O.
Wang Yun
Jones Allston L.
Nelms David
Nhu David
Ultratech Stepper, Inc.
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