High speed semiconductor memory having a direct-bypass signal pa

Details High speed semiconductor memory having a direct-bypass signal pa High speed semiconductor memory having a direct-bypass signal pa

1992-01-21

1992-09-08

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, 365233, G11C 700, G11C 800

Patent

active

051464276

ABSTRACT:
In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and the inputs of the data output buffer. The outputs of the sense amplifier are transmitted to the inputs of the data output buffer through signal paths which bypass the first pass-gates, the latch circuit and the second pass-gates, whereby the data output buffer generates a data output quickly. Thereafter, the first pass-gates and the second pass-gates are controllably brought to a signal-through condition, whereby the output information items of the sense amplifier are stored in the latch circuit. The data output buffer holds the data output in conformity with the stored information items of the latch circuit. For a period of time for which the data output buffer holds the data output, the sense amplifier is held in a non-activated condition, so that the power consumption of the semiconductor memory is lowered.

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Minato et al, "A 42ns 1Mb CMOS SRAM", IEEE-ISSC '87 (Feb. 27, 1987), Dig. of Techical Papers.
Yamamoto et al, "A 256K CMOS SRAM with Variable-Impedance Loads", IEEE-ISSC '85 (Feb. 13, 1985), Dig. of Technical Papers.

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