High speed semiconductor device with a metallic substrate

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257410, 257411, 257406, 257395, H01L 2701

Patent

active

056506503

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a semiconductor device, and in particular relates to a semiconductor which is capable of ultra high speed operation.


BACKGROUND ART

Presently, semiconductor integrated circuit technology is developing at an astonishing rate. Much of this amazing progress has come about due to the development of extremely small elements. By means of this great reduction in size of the elements, it has become possible to integrate a greater number of elements on a single chip, and as a result, it has become possible to realize a greater number of functions. Furthermore, a high operational speed has also been achieved as a result of the reduction in size of the elements.
The range in research into ultra high speed LSI has included research into various devices, such as very small CMOS elements, BiCMOS elements, heterobipolar elements, GaAs elements, Josephson elements, and the like. However, demands for ultra LSI at room temperatures are strong, and much is expected of silicon-based technologies in future semiconductor integrated circuit technology. Furthermore, when the reduction in logical swing resulting from the reduction in power source voltage accompanying the extreme reduction in the size of the elements, and the simplification of the manufacturing process, is taken into consideration, BiCMOS elements are also incapable of meeting the demands stated above, so that CMOS elements, which have superior symmetry in circuit operation and which permit a large noise margin, are indispensable in order to guarantee system reliability.
However, when conventional CMOS elements are employed, the power consumption, that is to say, the generation of heat, increases in proportion to the clock frequency, and this causes a problem in that the thermal noise level increases, and there is also the problem of the latch-up phenomenon.
The increase in the power consumption of the circuit resulting from high speed operation is a problem which is linked to the increase of temperature within the chip and to a deterioration in reliability and operational performance. If the thermal resistance of the circuit is represented by R.sub.t (.degree. C./W) the power consumption is represented by P(W), and the increase in temperature is represented by .DELTA.T(.degree.C.), then the relationship .DELTA.T=Rt.multidot.P obtains. If .DELTA.T is set to the allowable temperature increase of the circuit, then the smaller the value of Rt, the greater the possible value of P, and the higher the speed at which operation is possible. That is to say, in high speed circuit operations, it is necessary to reduce the thermal resistance in the circuit as much as possible.
It is a commonly known fact that the power driving capacity of a MOSFET increases with decreasing size. Formula (1) below shows the current/voltage relationship in the saturation region of the MOSFET. -V.sub.TH).sup.2 ( 1) film
Now, it will be assumed that the dimensions of the device are scaled down by a factor 1/.alpha. (.alpha.>1). Even if gate width W and gate length L are both reduced by the factor 1/.alpha., the drain current I.sub.D which enables driving does not change. On the other hand, if the thickness d.sub.ox of the gate oxide film is reduced by the factor 1/.alpha., the gate insulating film capacitance C.sub.ox increases by a factor .alpha., and the drain current I.sub.D enabling driving increases by the factor .alpha.. Furthermore, the load capacitance driven by this transistor (the normal gate capacitance) is expressed by C.sub.ox .multidot.L.multidot.W; however, this value is reduced by the factor 1/.alpha.. Accordingly, the amount of time necessary to charge or discharge the load capacitance is shortened by the factor 1/.alpha..sup.2. In this way, as a result of the increase in the current driving capacitance of the elements and the reduction in the load capacitance accompanying a great reduction in the size of the elements, higher speeds are attained.
However, at this point the pace of development towards decreasing element size h

REFERENCES:
patent: 5289027 (1994-02-01), Terrill et al.
patent: 5422505 (1995-06-01), Shirai

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