High-speed programmable interconnect

Details High-speed programmable interconnect High-speed programmable interconnect

2000-12-15

2002-05-07

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S040000

Reexamination Certificate

active

06384629

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the field of programmable logic devices, and more particularly, to interconnection resources for programmable logic devices.
Logic devices and methods of their operation are well known to those of skill in the art. Programmable logic devices have found particularly wide application as a result of their combined low up-front cost and versatility to the user. Altera's FLEX® line of programmable logic are among the most advanced and successful programmable logic devices. The FLEX architecture provides a large matrix of small logic elements (also known as macrocells) that can be programmably configured and interconnected to provide desired logic functions.
In many programmable logic devices, for example, a number of logic elements are arranged in groups to form larger entities referred to as logic array blocks (“LABs”). The various LABs are arranged in a two-dimensional array and are connectable to each other and to I/O pins of the device though continuous lines that run the entire length/width of the device. These lines are referred to as horizontal interconnect and vertical interconnect or collectively as “global” interconnect lines. In Altera's line of production these may include what are referred to as “Horizontal FastTracks™” and “Vertical FastTracks™.”
Each logic element can perform various combinational and registered logical operations. A local interconnect resource is also provided to allow the logic elements in a LAB to share signals without using the global interconnection resources. Additional detail regarding the FLEX devices may be found, for example, in Altera's Data Book, January 1998, along with U.S. Pat. Nos. 5,260,610 and 5,260,611, all of which are incorporated herein by reference for all purposes.
These logic devices have met with substantial success and are considered pioneering in the area of programmable logic. While pioneering in the industry, certain limitations still remain. For example, a large portion of the delay in the critical path is due to delay in the interconnect resources. A certain amount of delay exists in the connection between the global interconnect structure and the LABs. Thus a faster global interconnect can increase the overall system performance significantly.
Another aspect of programmable logic integrated circuits that may be improved is the programming flexibility of the interconnect resources in the logic device. In currently available devices, a signal may be routed from a vertical conductor to a horizontal conductor without passing through a logic element, but for a signal to be routed from a horizontal conductor to a vertical conductor, it must pass through a logic element. Also, currently available devices do not provide complete flexibility in routing between horizontal and vertical lines. For example, at a particular junction, a vertical conductor may only be connected to a single horizontal conductor. It is desirable to be able to select from among a plurality of vertical conductors as the destination, thereby increasing the routing flexibility of the logic device.
For at least the above reasons, a PLD which provides faster and more flexible interconnect resources is needed.
SUMMARY OF THE INVENTION
An improved programmable logic integrated circuit with high-speed interconnection resources and greater routability is described.
In accordance with a first aspect of the present invention, a faster interconnection between the horizontal interconnect resource and the local interconnect is provided. The local interconnect provides a path to the logic inputs of the logic elements. A signal regeneration circuit is provided in the path between horizontal conductors and the local interconnection. The signal regeneration circuit is preferably a pair of cross-coupled inverters that isolate the capacitance of the horizontal interconnect resource from the local interconnect, thereby allowing the switching to occur at a faster rate. It also boosts the signal allowing for faster switching operation.
In accordance with another aspect of the present invention, improved routability between the horizontal and vertical interconnects is described. A path is provided allowing the selective routing of signals from the horizontal interconnect to the vertical interconnect, without passing through a logic element. The horizontal interconnect may be selectively coupled to several of the vertical interconnect conductors in some embodiments.
In accordance with yet another aspect of the present invention, improved routability between the vertical and horizontal interconnects is described. A path is provided to allow a horizontal interconnect to be routed to any of a plurality of vertical interconnect conductors. In an embodiment, a multiplexer allows the selection from a plurality of horizontal interconnect conductors to be routed to the plurality of vertical interconnect conductors.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.


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