High-speed multiplexer latch

Details High-speed multiplexer latch High-speed multiplexer latch

2007-06-12

2007-06-12

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S189050, C365S203000, C326S086000, C327S407000

Reexamination Certificate

active

11259342

ABSTRACT:
Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer latch may further include an inverter having an input and an output. The input of the inverter is also coupled to the latch at the second node and the output of the inverter is coupled to a data output terminal. The multiplexer latch may further include a bypass circuit coupled to the latch at the first node and the data output terminal.

REFERENCES:
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patent: 6028448 (2000-02-01), Landry
patent: 6501696 (2002-12-01), Mnich et al.
patent: 6707741 (2004-03-01), Mnich et al.
patent: 6943589 (2005-09-01), Dobberphul
Cypress Semiconductor Corporation, “FLEx36™ 3.3V 32K/64K/128K/256K x36 Synchronous Dual-Port RAM”, Data Sheet, 29 pages, Document # 38-06070 Rev. *E, Revised Mar. 7, 2005.
Cypress Semiconductor Corporation, “FLEx36™ 3.3V 32K/64K/128K/256K x36 Synchronous Dual-Port RAM”, Data Sheet, 31 pages, Document #38-06070 Rev. *G, Revised Aug. 15, 2005.

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