Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1985-12-09
1988-12-20
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365233, 365239, 365194, G11C 700, G11C 800
Patent
active
047929260
ABSTRACT:
A high speed memory system for 100% bandwidth use with a control bus bearing contiguous sequentially intermixed data read and data write signals including a first buffer for reading data from a storage means into the data bus and a second buffer for writing data from the data bus into the storage means and a memory control sensitive to the order of received write requests and read requests signals to avoid any simultaneous utilization of the data bus and storage means in accordance with a prearranged schedule of preferential utilization of the data bus and storage means. The subject invention and related method further contemplates the employment of a plurality of input/output ports which are responsive to data read and/or data write request signals on the control bus for reading data from and/or writing data into the data bus in synchronism with the utilization of the first and second buffers.
REFERENCES:
patent: 3851313 (1974-11-01), Chang
patent: 4222102 (1980-09-01), Tansen et al.
patent: 4403308 (1983-09-01), Girard
patent: 4406013 (1983-09-01), Reese et al.
Fears Terrell W.
Kabushiki Kaisha Toshiba
Koval Melissa J.
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