High speed low noise transistor

Details High speed low noise transistor High speed low noise transistor

2001-10-19

2004-03-16

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S680000

Reexamination Certificate

active

06706583

ABSTRACT:

FIELD
The invention relates generally to the field of integrated circuit fabrication and, in particular, to heterojunction bipolar transistors.
BACKGROUND
The addition of germanium to silicon for forming silicon germanium semiconductor devices has provided introduction of heterojunction bipolar transistors which tend to operate at higher speeds than conventional silicon bipolar transistors. However, conventional bipolar transistors typically use a buried subcollector and a low resistivity sinker to reduce the resistance between the collector and the collector conductor on a semiconductor substrate. Deep trench isolation structure are typically used with such devices to reduce peripheral capacitance between the device and the substrate. For example, deep trench isolation structures tend to provide a reduction in the peripheral capacitance between the collector of the bipolar transistor and the substrate. However, the largest contributor to the overall capacitance of the device typically comes from the buried subcollector and the substrate. Deep trench isolation structures are substantially ineffective in reducing the capacitance between the subcollector and the substrate. Sinkers are also typically used with such bipolar transistor devices to connect the subcollector to a conductor region in order to reduce the collector resistance. However, for higher speed lower noise semiconductor devices additional improvements in capacitance and resistance are needed.
SUMMARY
The above and other needs are met by a method for making a heterojunction bipolar transistor on an insulated semiconductor substrate so as to minimize collector resistance and collector to substrate capacitance. A highly doped subcollector is formed in a subcollector region on an insulated substrate, and a collector region is defined adjacent the subcollector region. A lightly doped collector is formed adjacent to and in direct contact with the subcollector. A doped extrinsic base film stack is deposited on the lightly doped collector. The extrinsic base film stack is etched to provide a collector base and base emitter junction window in the extrinsic base film stack. A doped semiconductor intrinsic base is formed in the junction window. A self aligning base emitter spacer is deposited and etched in the junction window. The emitter material is deposited and etched in the junction window, and the emitter has emitter walls. Oxide spacers are deposited and etched adjacent the emitter walls of the emitter material. An extrinsic base is defined and conducting materials are deposited on the emitter and extrinsic base.
According to another aspect of the invention, a subcollector is laterally adjacent at least a portion of a collector so as to be in direct contact with each other. The subcollector and collector are disposed between shallow trench isolation structures on an insulated substrate.
In still another aspect of the invention, a lightly doped collector includes a first portion laterally adjacent a highly doped subcollector and a vertically grown portion adjacent the lateral portion. Both the lateral portion and the subcollector are disposed between shallow trench isolation structures on an insulated substrate.
By having the subcollector and collector in direct adjacent contact with one another, intermediate conducting materials are avoided, thereby preferably reducing the collector resistance. The collector to substrate capacitance is also preferably reduced by forming the bipolar transistor according to the invention on an insulated substrate and providing isolation structures adjacent the subcollector or collector.


REFERENCES:
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patent: 5620907 (1997-04-01), Jalali-Farahani et al.
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patent: 6191021 (2001-02-01), Fuller et al.
patent: 6426265 (2002-07-01), Chu et al.
patent: 6441462 (2002-08-01), Lanzeritti et al.

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