High speed input buffer

Details High speed input buffer High speed input buffer

1996-10-28

1999-02-16

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365207, 365205, 326 83, G11C 700

Patent

active

058727361

ABSTRACT:
A data bus is described which has integrated circuits, such as memory circuits, coupled thereto. The integrated circuits include an input buffer circuit adapted to receive and latch high speed data transmissions. The input buffer circuit equilibrates a sensing circuit, samples input data, senses the sampled input data, and latches the sensed data during different phases of an input clock cycle. An input buffer circuit is described which has two receiver circuits for receiving data transmissions having a higher speed data transmissions.

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