High speed input buffer

Details High speed input buffer High speed input buffer

1997-12-18

1999-06-08

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, G11C 700

Patent

active

059109203

ABSTRACT:
A data bus is described which has integrated circuits, such as memory circuits, coupled thereto. The integrated circuits include an input buffer circuit adapted to receive and latch high speed data transmissions. The input buffer circuit equilibrates a sensing circuit, samples input data, senses the sampled input data, and latches the sensed data during different phases of an input clock cycle. An input buffer circuit is described which has two receiver circuits for receiving data transmissions having a higher speed data transmissions.

REFERENCES:
patent: 4096402 (1978-06-01), Schroeder et al.
patent: 4404474 (1983-09-01), Dingwall
patent: 4638187 (1987-01-01), Boler et al.
patent: 4789796 (1988-12-01), Foss
patent: 4958088 (1990-09-01), Farah-bakhsh et al.
patent: 4984204 (1991-01-01), Sato et al.
patent: 5122690 (1992-06-01), Bianchi
patent: 5128560 (1992-07-01), Chern et al.
patent: 5128563 (1992-07-01), Hush et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5150186 (1992-09-01), Pinney et al.
patent: 5165046 (1992-11-01), Hesson
patent: 5179298 (1993-01-01), Hirano et al.
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5220208 (1993-06-01), Schenck
patent: 5239206 (1993-08-01), Yanai
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5274276 (1993-12-01), Casper et al.
patent: 5278460 (1994-01-01), Casper
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 5311481 (1994-05-01), Casper et al.
patent: 5321368 (1994-06-01), Hoelzle
patent: 5347177 (1994-09-01), Lipp
patent: 5347179 (1994-09-01), Casper et al.
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 5361002 (1994-11-01), Casper
patent: 5381364 (1995-01-01), Chern et al.
patent: 5400283 (1995-03-01), Raad
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5438545 (1995-08-01), Sim
patent: 5440260 (1995-08-01), Hayashi et al.
patent: 5451898 (1995-09-01), Johnson
patent: 5457407 (1995-10-01), Shu et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5488321 (1996-01-01), Johnson
patent: 5497127 (1996-03-01), Sauer
patent: 5498990 (1996-03-01), Leung et al.
patent: 5513327 (1996-04-01), Farnwald et al.
patent: 5568077 (1996-10-01), Sato et al.
patent: 5574698 (1996-11-01), Raad
patent: 5576645 (1996-11-01), Farwell
patent: 5578941 (1996-11-01), Sher et al.
patent: 5581197 (1996-12-01), Motley et al.
patent: 5589788 (1996-12-01), Goto
patent: 5621340 (1997-04-01), Lee et al.
patent: 5627780 (1997-05-01), Malhi
patent: 5684749 (1997-11-01), Seyyedy et al.
patent: 5694065 (1997-12-01), Hamasaki et al.
Chapman, et al., "A Low-Cost High-Performance CMOS Timing Vernier for ATE", IEEE International Test Conference, 459-468, (1995).
Descriptive literature entitled, "400MHz SLDRAM 4M X 16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," SLDRAM Consortium Advance Sheet, published throughtout the United States, pp. 1-22.
"Draft Standard for a High-Speed Memory Interface (SyncLink)", Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996, by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.
Ljuslin, et al., "An Integrated 16-Channel CMOS Time to Digital Converter", Nuclear Science Symposium & Medical Imaging Conference vol. 1, IEEE Conference Record, 625-629, (1993).

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