Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1998-08-07
2001-03-06
Wiley, David A. (Department: 2155)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S120000
Reexamination Certificate
active
06199121
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to the field of direct memory access (“DMA”) and, in particular, to dynamic chaining of DMA operations.
DMA operations facilitate transference of data from a source (e.g., a memory, input/output (I/O) device, etc.) to a destination (e.g., another memory, I/O device, etc.) without requiring a host processor to control the data transfer itself. Transfers may be between like or different device types (e.g., memory-memory, memory-I/O device, etc.). In a DMA operation, the host processor initially provides information to a DMA controller (also referred to as a “Bus Master”) specifying the parameters of a data-transfer operation (e.g., the address of a block of data to be transferred, the amount of such data, the destination address, etc.; referred to collectively herein as “data-transfer parameters”). The DMA controller, thereafter, handles the actual data transfer.
When performing DMA operations, the DMA controller gains control of an interconnecting bus (or busses) between the source and destination devices. The controller receives data-transfer parameters from a host processor and notifies the processor when the operation has been completed. One well-known method for conveying data-transfer parameters between a processor and DMA controller is through “channel control blocks” or “descriptors” (referred to herein as “control blocks”); i.e., data structures created by the processor, stored in a memory and accessed by the DMA controller for effecting a particular DMA operation.
To facilitate the execution of multiple DMA operations in succession, it is known to “chain” such operations together by constructing a linked list of corresponding control blocks. The linked list may be created through memory addresses; i.e., each block contains the address of the block disposed immediately subsequent in the chain. (Such memory address is referred to herein as a “link address,” a “next control block pointer” or simply a “block pointer.”) In conventional designs, a “chain bit” may be held in each control block to indicate whether a block currently undergoing processing is linked to a subsequent block. Under such circumstances, the host processor may be required to poll this bit to determine whether a chaining operation is to be carried out. Such polling may contribute to bus traffic in the system.
Often, while a DMA controller is performing a data transfer operation specified by a particular control block, the host processor specifies additional data transference operations by creating additional control blocks. When additional control blocks are created, it is desirable to append the new control blocks to the existing linked list of control blocks to allow the DMA controller to process all the control blocks in one uninterrupted sequence of data-transfer operations. Without the ability to append such control blocks, the DMA controller will deactivate upon completion of the data-transfer operation specified by the original linked list. Then, the host processor will need to restart the DMA controller to handle the data transfer operation specified by the new group of control blocks. Such operation of deactivating and restarting the DMA controller may result in significant time delays and should be avoided when possible.
The appending of control block(s) to an existing block (or linked-list of blocks) before a corresponding DMA operation is complete is referred to herein as dynamic chaining of DMA operations (“dynamic DMA chaining”). Linked lists of control blocks (also referred to herein as “chains” or “control-block chains”) that allow such appending of additional control blocks are considered “dynamic”. In contrast, chains that are defined prior to the start of a corresponding DMA operation and cannot be appended to before such operation is complete are considered “static”.
The transfer of high-speed streaming data (such as audio data in DVD or CD-ROM technologies) requires frequent dynamic DMA chaining. At least one known implementation of dynamic DMA chaining, however, suffers from poor performances as the DMA controller actually suspends operations during the chaining process in order to prevent race conditions. The term “race condition” as used herein, refers to a situation where data (i.e., a control block) can be inadvertently omitted from its intended position within a given sequence of data transference operations (and thereby missed during processing) due to the timing of at least two events. Such condition may arise, for example, when a current control block in a chain is processed before new block(s), intended to be processed before the current block, can be timely inserted in the current control-block chain. Accordingly, it would be desirable to facilitate dynamic chaining of DMA operations without suspending the controller or incurring such race conditions.
In another known implementation of dynamic DMA chaining, a DMA controller must access a memory twice to fetch and update information held in a given control block at least each time dynamic DMA chaining occurs. The update is to obtain the block pointer of appended block(s) for a current block being processed. It would be further desirable to reduce or eliminate the need to provide such frequent updates of block pointers.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus is provided for dynamic chaining of DMA operations without suspending a DMA controller or incurring race conditions. Certain embodiments of such method and apparatus also reduce or eliminate the need for updating a block pointer of a control block being processed.
In one embodiment, a system for transferring data is provided which includes a data bus and a controller that effects a transfer of data on the data bus, such controller operating in accordance with a current control block containing data-transfer parameters. The system also includes a processor coupled to the controller, such processor providing one or more new control blocks while the controller is effecting the transfer of data in accordance with the current control block, such one or more new control blocks being accessed by the controller after the current control block. Additionally, disposed within the controller is a counter which maintains a current count associated with the one or more new control blocks.
In another embodiment, a method is provided for performing a data transfer under the control of a DMA controller. This method includes the preallocating of a portion of memory to hold a plurality of anticipated control blocks, the plurality of such control blocks being associated through a predefined linked list. In addition, the method includes generating an initial control-block chain from a first portion of the anticipated control blocks; transferring data in accordance with data-transfer parameters disposed in the initial control-block chain; checking a count value to determine whether any other control blocks in another control-block chain are awaiting processing after effecting data transfer in accordance with the initial control-block chain; and continuing data transfer when the count value indicates other control blocks are awaiting processing, and otherwise waiting for the other control blocks to be generated.
In yet another embodiment, a system for transferring data is provided which includes a memory that holds a plurality of complete control blocks, the plurality of such control blocks being organized into a plurality of control-block chains. Also included are a device (coupled to the memory) which is capable of storing data; a DMA controller that effects a transfer of data between the memory and the device, such controller operating in accordance with one of the plurality of complete control blocks; and a counter, disposed in the DMA controller, that contains a count indicating a quantity of remaining control-block information to be processed.
A further understanding of the nature and advantages of the invention may be realized by reference to the remaining portions of the specification
Olson Steven E.
Shaw Jhy-Ping
Oak Technology, Inc.
Townsend and Townsend / and Crew LLP
Wiley David A.
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