High speed differential sense amplifier for use with single tran

Details High speed differential sense amplifier for use with single tran High speed differential sense amplifier for use with single tran

1991-05-06

1992-05-26

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Precharge

365202, 365185, 365208, 365210, G11C 1606

Patent

active

051173948

ABSTRACT:
A memory circuit incorporates a differential sense amplifier to be utilized in conjunction with a memory array comprised of a plurality of memory cells each containing a single transistor. A high slew rate differential input signal is applied to the sense amplifier based upon the binary data stored in an addressed memory cell. This is accomplished by pre-charging the selected bit line and a reference bit line, and then selecting the word line of the memory cell to be read, while causing the reference memory cell to conduct. The differential voltage between the selected bit line and the reference bit line is then sensed to determine the state of the data stored in the selected memory cell. The ratio of currents through the selected bit line and the reference bit line is selected to be other than one, in order to achieve a rapid differential voltage swing, and rapid reading of the data stored within the selected memory cell.

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patent: 4903237 (1990-02-01), Rao
"The Technology of a 1MBIT CMOS EPROM", by G. Nelmes, New Electronics, vol. 18, No. 22, Nov. 1985, pp. 70-74.
"A 1MB CMOS EPROM with Enhanced Verification", by D. Novosel et al., 1988 IEEE Solid-State Circuits Conference, Digest of Technical Papers, 17th-19th Feb. 1988, pp. 124-125, 325.

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