High speed data transfer for a semiconductor memory

Details High speed data transfer for a semiconductor memory High speed data transfer for a semiconductor memory

1980-10-10

1982-08-10

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365189, G11C 1300

Patent

active

043441564

ABSTRACT:
A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches. In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch outputs its stored data. The process continues with each decoder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.

REFERENCES:
patent: 4254477 (1981-03-01), Hsia et al.
patent: 4279023 (1981-07-01), Houghton

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