High-speed data latch with zero data hold time

Details High-speed data latch with zero data hold time High-speed data latch with zero data hold time

1988-01-22

1989-07-04

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365190, 365205, 307530, G11C 1300

Patent

active

048456756

ABSTRACT:
A data latch with substantially zero hold time and with immunity to input data changes occurring after the latch has slewed toward a definable logic state. An input data flip-flop (10) is coupled via transfer transistors (40, 42) to an output data flip-flop (12). Output nodes (36,38) of the output data flip-flop (12) are prechargeable. Inhibit transistors (24,30) are cross-coupled between the input data flip-flop (10) and the output data flip-flop (12) to prevent input data changes from affecting the latch once the output data flip-flop (12) slews toward a definable stable state.

REFERENCES:
patent: 4740926 (1988-04-01), Takemae et al.

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