High speed data buffer using a virtual first-in-first-out regist

Details High speed data buffer using a virtual first-in-first-out regist High speed data buffer using a virtual first-in-first-out regist

1998-08-31

2000-02-15

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365221, 36523005, 36523009, G11C 700

Patent

active

060260327

ABSTRACT:
A dual-port, static random access memory (DPSRAM) is configured as a virtual first-in-first-out (FIFO) register under the control of a microprocessor executing a stored program or similar circuit to allow both for conventional random access data buffering between the data source and the data receiver and FIFO-type data buffering in which the data source and data receiver need not generate an address for each data word transferred, but these addresses may be automatically generated in sequence by the buffer using special circuitry.

REFERENCES:
patent: 5420984 (1995-05-01), Good et al.
patent: 5487049 (1996-01-01), Hang
patent: 5787454 (1998-07-01), Rohlman
patent: 5825692 (1998-10-01), Baumgartner et al.

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