High speed CMOS output buffer circuit minimizes propagation dela

Details High speed CMOS output buffer circuit minimizes propagation dela High speed CMOS output buffer circuit minimizes propagation dela

1993-09-28

1995-08-01

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 17, 326 83, H03K 1716, H03K 190175

Patent

active

054382785

ABSTRACT:
An output buffer circuit is disclosed that minimizes propagation delay and crowbar current. This circuit receives a data input signal and provides an output signal. This circuit includes a pull-up transistor, a first pull-down transistor, a speed improvement circuit and a crowbar current reduction circuit. The speed improvement circuit comprises an inverter with small propagation delay coupled to a second pull-down transistor which is smaller than the first pull-down transistor. The speed improvement circuit minimizes the propagation delay of the circuit when the data input signals changes from a high logic level to a low logic level by speeding up the initial rate of fall of the output signal due to the fast turning on of the second small pull-down transistor which receives the data input signal quickly through the small-propagation-delay inverter. The crowbar current reduction circuit comprises a first crowbar current reduction transistor which is smaller than the pull-up transistor. The crowbar current reduction circuit minimizes the crowbar current through the pull-up transistor and the first pull-down transistor when the data input signals changes from a high logic level to a low logic level by speeding up the turning off of the pull-up transistor due to the fast turning on of the small first crowbar current reduction transistor which receives the data input signal quickly through the small-propagation-delay inverter. A split Ground metal bus and a split package lead are used for minimizing noise.

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