High speed addressing buffer and methods for implementing same

Details High speed addressing buffer and methods for implementing same High speed addressing buffer and methods for implementing same

1997-04-21

1999-03-23

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365196, 36523008, G11C 700

Patent

active

058869298

ABSTRACT:
Disclosed is an apparatus for generating a memory access signal. The apparatus includes a latch having a set state for driving a set transistor, and a reset state for driving a reset transistor. The latch having an input terminal and an output terminal, and the latch transitions between the set and reset states in accordance with a system clock signal. The apparatus further includes a driver coupled to the output terminal of the latch for producing an access signal, and feedback path for feeding back the access signal to the input terminal of the latch. Wherein the latch operates to switch from the set state to the reset state in accordance with the fed back access signal. In this manner, the system clock is isolated from the set transistor when the latch is already in the set state. Further, the latch operates to switch from the reset state to the set state in accordance with the fed back access signal, such that the system clock is isolated from the reset transistor when the latch is already in the reset state.

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