High selectivity etching process for metal gate N/P patterning

Details High selectivity etching process for metal gate N/P patterning High selectivity etching process for metal gate N/P patterning

2009-06-05

2010-06-08

Garber, Charles D (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S705000, C438S706000, C438S745000, C438S942000, C257SE21023, C257SE21218, C257SE21219

Reexamination Certificate

active

07732344

ABSTRACT:
A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.

REFERENCES:
patent: 6995095 (2006-02-01), Yu
patent: 7611943 (2009-11-01), Liu
patent: 2009/0075441 (2009-03-01), Chou et al.

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