Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-11
2001-08-21
NIebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S304000, C438S595000, C438S596000
Reexamination Certificate
active
06277700
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally to a process for etching silicon nitride (SiN) spacers on sidewalls of gate electrodes of semiconductor devices.
2) Description of the Prior Art
Spacers are widely used in manufacturing as protective structure against subsequent processing steps. In particular, nitride spacers formed beside gate electrodes are used as a mask to protect underlying source/drain areas during doping or implanting steps.
As physical geometry of semiconductor devices shrinks, the gate electrode spacer becomes smaller and smaller. The spacer width is limited by nitride thickness that can be deposited conformably over the dense gate electrodes lines. So the nitride spacers etching process is preferred to have a high ratio of spacer width to nitride layer thickness as deposited (we call this ratio the width to thickness ratio). At the same time high selectivity or nitride to oxide is required to prevent damage on silicon substrate. The conventional F based chemistry gives relatively high selectivity, but low width thickness ratio. The existing Cl based chemistry gives relatively high width to thickness ratio but low selectivity.
The patent of Babie et al. (U.S. Pat. No. 5,431,772, July 1995) described a two-step method of etching silicon nitride film, and was mainly concerned with the problem of possible contamination of the surface of the silicon nitride film by oxygen-containing substances such as silicon dioxide or silicon oxynitride. That invention comprises a first step of removing the surface oxide or oxynitride from the silicon nitride layer in a reactive plasma of fluorine-containing gases consisting essentially of SF
6
, CF
4
, C
2
F
6
and NF
3
. In the second step, the main etch: step, the silicon nitride layer is etched with a high selectivity with respect to the etching of the silicon dioxide underlayer, using a reactive plasma gas mixture of HBr, or HBr and SiF4, and an oxidant selected from the group consisting of O
2
, CO
2
, or N
2
O and a diluent gas such as He, N2, or Ar. The optimum process conditions are described to be as follows: HBr flow 20.00 sccm, O
2
flow 0.45 sccm, He flow 1.05 sccm, pressure 100 mTorr, power density 1.65 W/cm.sup.2, magnetic field 45 gauss, giving an etch rate of 600 ANG./min. They have mentioned a Si
3
N
4
/SiO
2
etch selectivity of 12.6:1.
Other prior art inventions have also described silicon nitride etch processes with high selectivities with respect to silicon dioxide underlayer.
In the fabrication of all kinds of integrated circuit devices, a high Si3 N4/SiO2 etch selectivity is important for accurately controlling the etch end point and preventing damage to the silicon substrate by over etching the oxide. The enhancement of the Si
3
N
4
/SiO2 etch selectivity is the aim of the prior art inventions mentioned above. However, these prior art inventions have not addressed issues that become very important in the fabrication of submicron devices, and particularly devices that are 0.5 &mgr;m or smaller. A very important issue is the requirement of the ability of the etch process to accurately conform to the critical dimension of these small devices. A very high degree of etch anisotropy is desirable to produce highly vertical sidewalls of the silicon nitride spacer, thereby conforming to the critical dimension from the top to the bottom of the silicon nitride spacer. A low etch anisotropy will produce undesirable sloping sidewalls of the silicon nitride layer, causing deviation from the required critical dimension and a low width to thickness ratio (less than 0.9).
Beside the silicon nitride etch processes described by the aforementioned prior art inventions, traditional nitride etch process currently in use is a two-step process comprising a main step using SF6 and He in the gaseous plasma to get near the end point, and a second step of high Si
3
N
4
/SiO
2
etch selectivity using SF
6
and O
2
in the gaseous plasma so as to prevent the occurrence of non-uniform patches of unremoved silicon nitride without unduly over-etching the pad oxide underneath the silicon nitride. Thus, the second etch step is an over-etch step for silicon nitride, but is one that will not over etch the pad oxide.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,431,772(Babie et al.) shows a SiN etch using O
2
/HBr and He.
U.S. Pat. No. 4,818,715(Chao) shows a poly gate stack etch with a SiN layer 42. See Col. 6.
U.S. Pat. No. 5,854,136(Huang et al.) shows a three step etch process with HBr, SF
6
and He.
U.S. Pat. No. 5,338,395(Keller et al.) shows another SiN etch process.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method to etch silicon nitride (SiN) spacers beside a gate electrode to maintain a good selectivity.
It is an object of the present invention to provide a method to etch SiN spacers beside a gate electrode to maintain a good selectivity and a good spacer width to SiN layer thickness ratio.
It is an object of this invention to provide a new etching process, capable of etching silicon nitride over SiO
2
very selectively for products where the semiconductor device structure would have an even thinner SiO
2
stopping layer during silicon nitride etching where it is required to assure product manufacturability and acceptable yield capacity in manufacturing.
It is an object of the present invention to provide a method for a SiN spacer etch comprising a chemistry comprising Cl
2
/He/HBr.
To accomplish the above objectives, the present invention provides a method of etching SiN layers to form spacers, where the etch has a high selectivity (>18:1 (SiN:SiO
2
) and about 20:1 (SiN to silicon oxide) and will not pit the Si substrate surface. The etch also has a high spacer width to thickness ratio. The main etch step preferably comprises Cl
2
/He and a low flow of HBr. The etch process employs main etch step with an end point detection and an overetch step that is a percentage of the main etch.
The invention is a method of etching silicon nitride spacers beside a gate structure comprising: providing gate electrode over a gate oxide layer on a substrate; providing a liner oxide layer over the substrate and the gate electrode; providing a silicon nitride layer over the liner oxide layer. The nitride layer is preferably formed by a PECVD, LPCVD or rapid thermal CVD(RTCVD) process.
A nitride etch recipe is performed in a plasma etcher to anisotropically etch the silicon nitride layer to create spacers. The nitride etch recipe comprises a main etch step and an over etch step. The main etch step comprising the following conditions: a Cl
2
flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, and a HBr flow between 7.5 and 12.5 molar %; a pressure between 400 to 900 mTorr and a backside cooling He pressure between 4 and 10 torr, and at a power between 300 and 600 Watts. The mole % (molar % flow rates or ratios) above do not include the small He backside cooling flow.
The mixed chemistry etch of the invention provides excellent selectivity to prevent Si Substrate pitting as well as anisotropic etch capability to ensure a good spacer width to SiN layer thickness ratio about 1.
A preferred set of etch conditions for a 4428XL model and LAM research REI etcher) is shown below. Of course these parameters will vary depending on the make and model of the etcher used in the process. The molar % rates or ratios of the gasses will remain the same and the process flow rates can be scaled up or down depending on the etcher and product.
Pressure 400 to 900 mtorr
Power: 300 to 600 Watts
Cl
2
: 50 to 200 SCCM (Standard cc per minute)
HE 50 to 200 SCCM
HBr 10 to 50 SCCM
He (Backside cooling pressure) 4 to 10 torr
Of course these parameters will va
Pradeep Yelehanka Ramachandramurthy
Wu Guan Ping
Yu Jie
Chartered Semiconductor Manufacturing Ltd.
Gurley Lynne A.
Niebling John F.
Pike Rosemary L. S.
Saile George O.
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