Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-12-06
2003-06-24
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S412000, C438S406000, C257S140000, C257S142000, C257S313000, C257S296000, C428S209000
Reexamination Certificate
active
06583024
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of producing a high-resistivity silicon wafer. More particularly, the present invention relates to a method of producing a high-resistivity, large-thickness epitaxial layer which is substantially free of oxygen thermal donors.
BACKGROUND OF THE INVENTION
High resistivity silicon wafers have conventionally been used for power devices such as high-voltage power devices and thyristors. More recently, C-MOS devices, Schottky barrier diodes, and other semiconductor devices for use in mobile communications have been developed which require the use of high-resistivity silicon wafers. The high-resistivity wafers tend to decrease the effects of parasitic capacitance among the devices of the wafer, allowing the devices to be more closely packed upon the surface of the wafer while, at the same time, reducing signal transmission loss among the devices.
High-resistivity wafers are generally defined as those silicon wafers with resistivity of 100 &OHgr;·cm or greater, and typically have resistivity of 1000 &OHgr;·cm. The initial resistivity of a wafer is established during crystal growth by the precise addition of dopants to the molten polysilicon from which the silicon crystal is formed. By doping, the resistivity of the crystals can be controlled within close tolerances. However, the initial resistivity may be altered, desirably or undesirably, during subsequent processing of the wafer such that the final resistivity of the wafer may be very different from the resistivity directly after crystal growth.
High-resistivity wafers are typically produced using the Czochralski (CZ) crystal growing method. The CZ method allows wafers having diameters of 200 mm, 300 mm, 400 mm, or larger to be produced. In addition to the large wafer diameter, the CZ method also provides wafers with excellent planar and radial resistivity distribution and lower cost. Good planar resistivity distribution means that the wafer has only minimal variations in resistivity along the plane which was perpendicular to the growth direction of the crystal during crystal growth.
Unfortunately, there are some problems related to the presence of oxygen during the growth of high-resistivity silicon wafers in a CZ apparatus. During crystal growth within a CZ apparatus, oxygen from the quartz crucible tends to be introduced into the silicon crystal and is maintained in the interstitial sites of the silicon crystal lattice. The interstitial oxygen atoms are normally electrically neutral, but the oxygen atoms tend to agglomerate as oxygen-containing thermal donors (OTDs), which become electron donors when subjected to heat in the range of 350° C. to 500° C. Thus, the resistivity of the wafer may be unfavorably decreased by a relatively mild heating due to the contribution of electrons from the OTDs residing in the wafer. The decrease in resistivity due to the oxygen is especially problematic considering that temperatures in the range of 350° C. to 500° C. are commonly encountered during process steps subsequent to wafer fabrication, such as during device fabrication.
As described in European Patent Office publication EP 1087041 A1, there is known a method of producing a high-resistivity wafer having a high gettering effect while preventing the reduction of resistivity due to electrons being donated from OTDs upon subsequent heating cycles of the wafer. The method includes first producing a single crystal ingot having a resistivity of 100 &OHgr;·cm or greater and an initial interstitial oxygen concentration of 10 to 25 parts per million atomic (ppma) by a CZ method. Interstitial oxygen is then precipitated with a gettering heat treatment step until the residual interstitial oxygen concentration in the wafer becomes about 8 ppma or less. The precipitated oxygen does not have the ability to donate electrons like the OTDs formed from the interstitial oxygen so subsequent heat treating processes do not result in a reduction in resistivity. The use of the gettering heat treatment step is capable of reducing the oxygen content of a 100 &OHgr;·cm wafer from 10 to 25 ppma to 8 ppma or less while generating or maintaining a bulk defect density of 1×10
8
to 2×10
10
defects/cm
3
.
The technique of using oxygen precipitation heat treatments to diminish thermal donors within the silicon crystal suffers from two drawbacks. The main drawback with the above described heat treatment is the process time and overall power requirements necessary to precipitate the oxygen within the wafer. Typically, for example, the heat treatment process may require a first heating step of 800° C. for 4 hours, a second heat treating step of 1000° C. for 10 hours, and a third heat treatment step of 1050° C. for 6 hours. Secondly, minimal amounts of interstitial oxygen do remain within the crystal after heat treatment and may contribute to minor fluctuations in resistivity within the wafer caused by heat treatments subsequent to the oxygen precipitation heat treatment process.
What is needed is a method of providing a high-resistivity material which does not require extended processing time and high energy thermal inputs and which does not contain appreciable amounts of residual interstitial oxygen within the silicon lattice.
SUMMARY OF THE INVENTION
The invention is a silicon wafer having a thick, high-resistivity epitaxially grown layer and a method of depositing a thick, high-resistivity epitaxial layer upon a silicon substrate. The epitaxial layer is substantially oxygen free and, therefore, thermal donation from interstitial oxygen atoms does not alter resistivity during heat treatment of the epitaxial layer or the underlying silicon substrate.
A method of obtaining a wafer exhibiting high resistivity while avoiding the reduction of resistivity due to the generation of oxygen donors is accomplished by: a) providing a silicon wafer substrate and b) depositing a substantially oxygen free, high-resistivity epitaxial layer, with a thickness of at least 50 &mgr;m, upon the surface of the silicon wafer. The high-resistivity epitaxial layer has a resistivity of at least 100 &OHgr;·cm and preferably greater than 1000 &OHgr;·cm.
The resulting wafer has high-resistivity in the region surrounding the semiconductor devices fabricated within the surface of the wafer. Also, the region of the wafer surrounding the devices has a very stable resistivity because no oxygen is present in the epitaxial layer.
After growth of the high-resistivity epitaxial layer, the epitaxial layer is optionally separated from the silicon substrate, leaving a high-resistivity silicon material which has been grown completely by epitaxial deposition and which has very low oxygen content.
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Kononchuk Oleg V.
Koveshnikov Sergei V.
Radzimski Zbigniew J.
Weaver Neil A.
Alston & Bird LLP
SEH America Inc.
Smith Matthew
Yevsikov V.
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