High reliability triple redundant memory element with...

Details High reliability triple redundant memory element with... High reliability triple redundant memory element with...

2006-04-11

2006-04-11

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S063000, C365S154000, C365S189080, C365S194000, C365S206000, C327S057000, C327S064000, C327S076000, C714S006130, C714S797000, C714S820000

Reexamination Certificate

active

07027333

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch with integrated testability. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements, determine the logical value held on each of the settable memory elements. Data may be scanned into and out of the second settable memory element. Data is propagated through the buffer into the third settable memory element. The third settable memory element may be used to scan data out of the triple redundant latch. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

REFERENCES:
patent: 6937527 (2005-08-01), Lotz et al.
patent: 2005/0127971 (2005-06-01), Hoff
patent: 2005/0251729 (2005-11-01), Lotz et al.

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