High reliability triple redundant latch with voting logic on...

Details High reliability triple redundant latch with voting logic on... High reliability triple redundant latch with voting logic on...

2005-08-30

2005-08-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S201000, C714S797000, C714S799000, C327S199000

Reexamination Certificate

active

06937527

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

REFERENCES:
patent: 2002/0095641 (2002-07-01), Cartagena
patent: 2004/0015754 (2004-01-01), Callaway et al.

Affiliated with

Also associated with

Rating

High reliability triple redundant latch with voting logic on... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High reliability triple redundant latch with voting logic on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High reliability triple redundant latch with voting logic on... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3508967