Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Fluid growth step with preceding and subsequent diverse...
Reexamination Certificate
1998-06-19
2001-07-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Fluid growth step with preceding and subsequent diverse...
C438S492000, C438S590000, C438S681000, C438S758000, C438S763000, C438S767000, C438S797000
Reexamination Certificate
active
06261931
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of this invention relate generally to gallium nitride (GaN) films, and in particular embodiments to methods for for forming high quality, semi-insulating GaN for reducing parasitic conductivity and parasitic capacitance in electronic devices, and systems incorporating the same.
2. Description of Related Art
In the fabrication of semiconductor devices such as light emitting diodes (LEDs), lasers, or field-effect transistors (FETs) there is often a need to create semiconducting layers with different physical and electrical properties to produce desired device performance. In FETs, for example, the transistor must be built upon a material with electrically insulative properties. Referring to
FIG. 1
, a FET
10
operates by having electrons
12
flow from one electrode (a “source”
14
) to another (a “drain”
16
), creating current flow
18
through the FET
10
, where the current flow
18
is modulated by third electrode (a “gate”
20
). The electrons
18
flowing from source
14
to drain
16
should ideally travel in a channel
22
close to the gate
20
to allow the gate
20
to control the current flow
18
. Thus, it is undesirable for electrons
12
to flow from source
14
to drain
16
in an arcing path
24
that travels a great distance from the gate
20
, or from source
14
along a parasitic path
26
to an entirely different location such as a ground
28
, because control over the electrons
12
is lost. For proper functioning of a FET
10
, the channel
22
must therefore be insulated to block these parasitic current flows.
Thus, a semi-insulating layer
30
(a layer that does not normally conduct current) is typically fabricated below the channel
22
to keep electrons
12
in the channel
22
and prevent them from taking paths
24
or
26
. Semi-insulating material blocks the flow of current through the material and is used in transistors where current must be allowed to flow in the channel, but not in the layer beneath it.
High-frequency operation is another reason for utilizing a semi-insulating underlayer
30
. In many present-day applications, transistors must operate at high frequencies. High frequency operation is dependent on minimizing the resistance R and capacitance C between circuit nodes and ground, because the larger the product of R and C (the “RC time constant”), the lower the frequency of possible circuit operation. There are two types of capacitance present on the gate
20
of FET
10
. A capacitance identified herein as a gate capacitance
32
exists between the gate
20
and the current-carrying electrons
12
. This gate capacitance
32
is necessary to modulate the current flow
18
under the gate
20
in the FET
10
. However, there is also a parasitic capacitance
34
that exists between the gate
20
and ground
28
through a resistive path
36
. The parasitic capacitance
34
should be minimized, because the RC time constant produced by the charging and discharging of the parasitic capacitance
34
through resistive path
36
slows down the operation of the gate
20
and FET
10
and also wastes power. Because of its insulating properties, the semi-insulating layer
30
prevents undesirable parasitic capacitance
34
from being generated on the gate
20
.
In certain applications, gallium arsenide (GaAs) and Indium phosphide (InP) have been used for semiconductor devices. GaAs and InP are typically grown as epitaxial layers over substrates of the same material (i.e., GaAs semi-insulating material is grown on available GaAs substrates, and InP semi-insulating material is grown on available InP). The growth of semi-insulating GaAs and InP on like substrates is preferable because crystal growth is simplified by the identical crystalline structure of the substrate and the material being grown.
In other applications such as the fabrication of high power or optoelectronic devices active in the ultraviolet (UV) to blue region of the electromagnetic spectrum, however, the properties of gallium nitride (GaN) make it preferable to GaAs or InP. Unfortunately, GaN substrates are not readily available, because it is very difficult to make GaN in bulk form.
Lacking a practical method of making bulk GaN upon which to grow semi-insulating GaN, sapphire or silicon carbide has often been selected as a substitute substrate material because of its similar terminal properties to GaN (very hard, high melting temperature), with sapphire being the predominant choice. However, growing GaN on a sapphire substrate is difficult, with its own set of unique problems and technology requirements that are not readily transferable from the fabrication processes of other semi-insulating materials.
The bonding of two dissimilar materials such as sapphire and GaN is made difficult because of their different crystalline structures. As illustrated symbolically in
FIG. 2
a
, GaN molecules
38
to be grown on a sapphire substrate
54
may first bond with each other to form a crystal
46
. When GaN molecules
38
bond together, the spacing of bonding atoms
42
(represented by dots in the comers of GaN molecules
38
) will align due to their identical atomic structures, and bonding is achieved without deformation of the GaN crystal
46
.
However, GaN molecules
38
must also bond with sapphire molecules
40
of the sapphire substrate
54
if a GaN layer is to be grown. Unfortunately, when a GaN molecule
38
attempts to bond with sapphire
40
, the gallium and nitrogen atoms
42
are not spaced in congruence with the aluminum and oxygen atoms
44
of the substrate (represented by dots in the corners of sapphire
40
). Notwithstanding this mismatch, because the atomic spacing of the GaN lattice and the atomic spacing of the sapphire lattice is not too dissimilar, the GaN crystal
46
will deform to complete the bond.
FIG. 2
b
illustrates a deformed GaN crystal
46
bonded with the sapphire substrate
54
, with the squeezed and stretched profiles of the GaN molecules
38
symbolically representing the stressed crystal structure. If this stress is large enough, the lattice of the GaN crystal
46
will start to tear.
FIG. 2
b
illustrates a torn GaN crystal
46
bonded with the sapphire substrate
54
. The tear in the GaN crystal
46
is known as a dislocation
52
.
Conventionally grown GaN on the surface of the sapphire substrate will have on the order of 10
10
dislocations per cm
2
. Because dislocations create defects of acceptor character which tend to absorb free electrons, this initial layer of GaN may be heavily insulating. Conventional techniques for growing GaN subsequently reduce the number of dislocations roughly an order of magnitude by during growth of the remainder of the GaN layer. If the growth of the remainder of the GaN layer is performed at reduced pressure (approximately 0.1 atm), the resultant GaN is semi-insulating not only because of the remaining dislocations, but also because carbon impurities introduced into the GaN during the growth process create point defects of acceptor character. Point defects near the surface of the GaN are undesirable if the GaN is used as an insulating layer for a FET, because they will capture electrons and inhibit the flow of current in the adjacent FET channel and will reduce the electron mobility in the channel.
High quality semi-insulating GaN, as defined herein, is characterized by high structural quality of the GaN (a relatively low number of dislocations) and high electronic quality at the atomic level (a low number of point defects). Conventional techniques therefore produce semi-insulating GaN of acceptable structural quality due to the reduction of dislocations during growth of the second layer, but of poor electronic quality due to the high concentrations of point defects generated during growth of the second layer.
SUMMARY OF THE DISCLOSURE
Therefore, it is an object of embodiments of the invention to provide a method for growing semi-insulating GaN of acceptable structural quality and high electronic quality.
It is a further object of embodiments of the
DenBaars Steven P.
Keller Bernd Peter
Keller Stacia
Mishra Umesh Kumar
Gates & Cooper LLP
Lee Granvill D.
Smith Matthew
The Regents of the University of California
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