High performance single port RAM generator architecture

Details High performance single port RAM generator architecture High performance single port RAM generator architecture

1993-11-30

1995-11-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365200, 365210, 364488, 364491, G11C 700

Patent

active

054714281

ABSTRACT:
A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure. The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.

REFERENCES:
patent: 4339766 (1982-07-01), Rao
patent: 4849935 (1989-07-01), Miyazawa
patent: 4926387 (1990-05-01), Madland
patent: 4982364 (1991-01-01), Iwahashi
Tou, Jarvis et al., "A Sub-Micron CMOS Embedded SRAM Compiler", IEEE 1991 Integrated Circuits Conference.
Dao, Tim et al., "A Dual-Port SRAM Compiler for 0.8mm 100K BICMOS Gate Arrays", IEEE 1991 Integrated Circuits Conference.
IBM Technical Disclosure Bulletin, vol. 31, No. 6, Nov. 1988, New York, US, pp. 128-129, "CMOS High Performance Sense Scheme for Growable Macros".

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