High performance RAM array circuit employing self-time clock gen

Details High performance RAM array circuit employing self-time clock gen High performance RAM array circuit employing self-time clock gen

1995-06-07

1997-04-08

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365233, G11C 1300

Patent

active

056194641

ABSTRACT:
A RAM array circuit is provided which includes a memory array formed by several RAM cell columns. A particular cell within each column and row may be selected for access (either read or write) by an address decode circuit. The RAM array circuit employs a self-time column having a delay characteristic which is approximately equal to that of each of the RAM cell columns. The rising edge of a single-phase clock is used to precharge each RAM cell column as well as the self-time column. As the self-time column is precharged to a high level, the self-time control circuit disables the precharge and enables the array access for read or write. When a particular row is selected by the address decoding mechanism, the self-time column is discharged. Once the self-time column has discharged, a sense amplifier is enabled to read data from the array. Access is then disabled and precharge is again enabled upon the next rising edge of the clock.

REFERENCES:
patent: 5270975 (1993-12-01), McAdams

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