High-performance PMOS transistor using a barrier implant in the

Details High-performance PMOS transistor using a barrier implant in the High-performance PMOS transistor using a barrier implant in the

1998-04-08

1999-03-16

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438528, H01L 21336, H01L 21425

Patent

active

058829741

ABSTRACT:
The present invention advantageously provides a method for forming a transistor having decreased source-side parasitic resistance and an improved shallow junction, thereby providing for enhanced transistor performance and improved resistance to short-channel effects. Barrier atoms are selectively implanted into the semiconductor substrate prior to formation of lightly doped drains and source/drain regions. Barrier atoms present in the channel region under the gate structure prevent migration of the lightly doped drain implant impurities into the channel region, thus reducing parasitic resistance. Barrier atoms implanted into the junction region prevent migration of source implant impurities more deeply into the junction region, thus preserving the shallow junction.

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J.M. Hwang et al, "High Performance Submicron SOI/CMOS With An Elevated Source/drain Structure", IEEE International SOI Conference Proceedings, 1993, pp. 132-133.
J.H. Lee et al., "Recessed Channel (RC) SOI NMOSFETs With Self-Aligned Polysilicon Gate Formed on the Region", IEEE International SOI Conference Proceedings, 1996, pp. 122-123.

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