Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-09-05
1999-11-30
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438303, 438305, 438307, H01L 218238
Patent
active
059941758
ABSTRACT:
A manufacturing process in which semiconductor transistors are fabricated using a fluorine or nitrogen implant into the n-channel regions and an amorphization implant to beneficially limit the spreading of the source/drain impurity distributions thereby decreasing the junction depth and increasing the sheet resistance of the source/drain regions. Broadly speaking, a gate dielectric layer is formed on a semiconductor substrate. First and second conductive gate structures are then formed on an upper surface of the gate dielectric layer. The first conductive gate is positioned over the p-well region while the second conductive gate is positioned over the n-well region. An n-channel mask is then formed on the substrate and a first impurity distribution is introduced into the p-well regions. The first impurity distribution preferably includes a species of fluorine or nitrogen. A n-type impurity distribution is then introduced into the p-well regions of the semiconductor substrate. A p-channel mask is then formed on the semiconductor substrate. After the p-channel mask is formed, a p-type impurity distribution such as boron is introduced into the n-well regions and into the second conductive gate structure. An electrically neutral impurity is then introduced into the semiconductor substrate to amorphize the semiconductor substrate to limit the subsequent redistribution of source/drain impurity distributions thereby resulting in the formation of shallow junctions. Thereafter, spacer structures are formed on sidewalls of the first and second conductive gate structures, and forming the spacer structures, n+ and p+ source/drain impurity distributions are introduced into the p and n well regions of the semiconductor substrate respectively.
REFERENCES:
Sze, S.M., Physics of Semiconductor Devices, John Wiley & Sons, Inc., New York, 1981, pp. 431-486.
Fulford H. Jim
Gardner Mark I.
Wristers Derick J.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Niebling John
Pham Long
LandOfFree
High performance MOSFET with low resistance design does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High performance MOSFET with low resistance design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance MOSFET with low resistance design will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1671108