Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-03-04
1999-09-14
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438185, 438305, 438306, H01L 21336
Patent
active
059536136
ABSTRACT:
The ultimate shallow source drain junction depth for a transistor is achieved by removing or detaching a source from the semiconductor substrate and forming an electron source on the surface of the semiconductor substrate adjacent to the transistor gate. The removal or detachment of an electron source from the semiconductor substrate eliminates the heavily-doped source drain diffusion or implant into a source region of the substrate, thereby avoiding non-uniform doping profiles that degrade long-channel subthreshold characteristics of a device as well as the punchthrough behavior of short-channel devices. A metal plug is used as an electron source which is removed or detached from the from the semiconductor substrate. The metal plug is vastly superior to doped semiconductor materials as an electron source. A method of fabricating an integrated circuit includes forming a lightly-doped drain (LDD) MOSFET structure prior to source/drain doping. The MOSFET structure includes a gate formed on a substrate over a gate oxide layer, spacers formed on sides of the gate, LDD doping of the substrate in a source region and a drain region self-aligned with the gate, and drain doping in the drain region self-aligned with the gate and spacers. The method further includes forming an oxide layer over the substrate and LDD MOSFET structure, forming a polysilicon layer over the oxide layer, cutting a via through the polysilicon layer and source layer to the substrate surface adjacent to the gate and spacer and abutting the source region of the substrate, and forming a metal plug in the via, the metal plug electrically coupling to the LDD doping in the source region of the substrate and electrically coupling to the polysilicon layer, the metal plug serving as a source for the MOSFET.
REFERENCES:
patent: 5747367 (1998-05-01), Kadosh et al.
patent: 5747373 (1998-05-01), Yu
patent: 5770482 (1998-06-01), Kadosh et al.
patent: 5783458 (1998-07-01), Kadosh et al.
Gardner Mark I.
Hause Frederick N.
Advanced Micro Devices , Inc.
Hack Jonathan
Koestner Ken J.
Niebling John F.
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