Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-06-26
2004-09-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S301000, C438S303000, C438S305000, C438S306000, C438S591000, C438S595000
Reexamination Certificate
active
06794258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a p-type MOS (Metal Oxide Semiconductor) transistor of LDD (Lightly Doped Drain-Source) structure and a manufacturing method thereof.
2. Description of the Related Art
Typical MOS transistors currently used in logic circuits and the like have an LDD structure as shown in FIG.
1
. Specifically, p-type MOS transistor
100
of LDD structure illustrated in
FIG. 1
is configured such that gate insulating film
102
in a predetermined pattern is disposed on the surface of n-type silicon substrate
101
, p-type gate electrode
103
is disposed thereon, and sidewalls
104
are formed on both sides of gate insulating film
102
and gate electrode
103
. Deeply doped p-type source/drain areas
105
are formed in the surface portions of silicon substrate
101
on the outer sides of the portions on which sidewalls
104
are formed. Lightly doped p-type source/drain areas
106
are formed in the surface portions of silicon substrate
101
on the inner sides of the deeply doped p-type source/drain areas
105
. Channel area
107
is interposed between paired lightly doped p-type source/drain areas
106
.
In the configuration, the interface between gate insulating film
102
and each sidewall
104
is close to the interface between channel area
107
and each source/drain area
106
. That is, MOS transistor
100
is configured such that the plane corresponding to the interface between gate insulating film
102
and each sidewall
104
substantially coincides with or opposite in close proximity to the plane corresponding to the interface between channel area
107
and each source/drain area
106
.
Since MOS transistor
100
configured as mentioned above has an LDD structure in which lightly doped source/drain areas
106
are located on the inner sides of deeply doped source/drain areas
105
, it can restrict the occurrence of hot carriers and prevent a reduction in breakdown voltage.
In the aforementioned MOS transistor
100
, gate insulating film
102
is formed of a silicon thermal oxidation film formed on the surface of silicon substrate
101
, and source/drain areas
105
,
106
and gate electrode
103
include a p-type impurity such as boron ion-implanted therein for allowing them to serve as p-channels.
A method of manufacturing MOS transistor
100
as described above is simply described in the following.
The surface of silicon substrate
101
is first subjected to thermal treatment to form a silicon thermal oxidation film on the entire surface. Gate electrode
103
in a predetermined pattern is formed on the surface of the silicon thermal oxidation film. Dry etching is performed on the silicon thermal oxidation film with gate electrode
103
used as a mask. The etching removes the portion of the silicon thermal oxidation film on the surface of silicon substrate
101
which is not masked by gate electrode
103
. The silicon thermal oxidation film remaining under gate electrode
103
is to serve as gate insulating film
102
.
Next, a p-type impurity is ion-implanted into gate electrode
103
to make gate electrode
103
p-type. A p-type impurity is ion-implanted into the silicon substrate at the positions where lightly doped source/drain areas
106
are to be formed and then annealing is performed for activation, thereby forming lightly doped source/drain areas
106
. Sidewalls
104
are formed on both sides of gate insulating film
102
and gate electrode
103
on the surface of the portions in silicon substrate
101
where source/drain areas
106
are formed. Finally, a p-type impurity is ion-implanted in the surface portions of silicon substrate
101
with sidewalls
104
used as masks and annealing is performed for activation to form deeply doped source/drain areas
105
. In this manner, p-type MOS transistor
100
of LDD structure is completed.
In the aforementioned transistor manufacturing method, lightly doped source/drain areas
106
are formed by implanting the p-type impurity into the surface portions of silicon substrate
101
with gate electrode
103
used as a mask and performing annealing, and deeply doped source/drain areas
105
are formed by implanting the p-type impurity into the surface portions of silicon substrate
101
with sidewalls
104
used as masks and performing annealing. Thus, it is possible to simply and reliably form the LDD structure including lightly doped source/drain areas
106
and deeply doped source/drain areas
105
.
In the aforementioned p-type MOS transistor
100
, however, when the impurity is implanted into silicon substrate
101
and then the annealing is performed to form source/drain areas
105
,
106
, the p-type impurity implanted into gate electrode
103
may be diffused even to channel area
107
in silicon substrate
101
through gate insulating film
102
. In this case, since channel area
107
in silicon substrate
101
which should be of n-type becomes p-type, the performance of p-type MOS transistor
100
is degraded.
To solve the problem, Japanese Patent Laid-open Publication No. 313114/98, for example, discloses a MOS transistor in which a gate insulating film is formed of a silicon oxynitride film to prevent a p-type impurity from being diffused to a channel area from a gate electrode.
The present inventors, however, have found, from actual manufacturing of a p-type MOS transistor having a gate insulating film formed of a silicon oxynitride film, that while it can prevent the diffusion of a p-type impurity from a gate electrode to a channel area, BT (Bias Temperature) characteristics show more degradation than that of one having a gate insulating film formed of a silicon thermal oxidation film. Studies to find a cause have revealed that the silicon oxynitride film contains positive fixed charge therein from the time of film formation, and the amount of the accumulated positive fixed charge is significantly increased due to BT stress to readily increase of the interface state density. Thus, a p-type MOS transistor having a gate insulating film formed of a silicon oxynitride film is susceptible to degradation of BT characteristics such as a shift of threshold voltage or degradation of on-state current.
In addition, detailed analysis of the BT characteristics have shown that a shift of threshold voltage or degradation of on-state current tends to occur due to fixed charge on both end portions of the gate insulating film close to source/drain areas, and the BT characteristics are affected to a lesser extent in the central portion of the gate insulating film away from the source/drain areas.
Accordingly, it is possible to prevent diffusion of a p-type impurity from a gate electrode to a channel area in a p-type MOS transistor and degradation of BT characteristics by forming the central portion of a gate insulating film of a silicon oxynitride film and forming each of both end portions of a silicon thermal oxidation film. A p-type MOS transistor of such structure is disclosed, for example, in Japanese Patent Laid-open Publication No. 102482/93. The p-type MOS transistor disclosed in the Laid-open publication has a structure including overlapping gate electrode and source/drain areas, in which the central portion of the gate insulating film is formed of a silicon oxynitride film while both end portions of the gate insulating film are each formed of a silicon thermal oxidation film. More (specifically, as shown in
FIG. 2
, p-type MOS transistor
120
disclosed in the aforementioned Laid-open publication has gate insulating film
122
and p-type gate electrode
123
disposed in turn on the surface of n-type silicon substrate
121
. Gate insulating film
122
is formed of silicon oxynitride film
128
only in the central portion, and formed of silicon thermal oxidation film
129
in each of both end portions. P-type deeply doped source/drain areas
125
and p-type lightly doped source/drain areas
126
are formed in the surface portions of silicon substrate
121
. Deeply doped source/drain areas
125
are primarily formed at the positions on the outer
Ando Koichi
Koyama Shin
Makabe Mariko
NEC Electronics Corporation
Niebling John F.
Roman Angel
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