High performance logic and high density embedded dram with...

Details High performance logic and high density embedded dram with... High performance logic and high density embedded dram with...

2002-05-31

2004-03-23

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S453000, C438S740000, C257S296000, C257S368000, C257S394000

Reexamination Certificate

active

06709926

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory cells for high integration density integrated circuits such as dynamic random access memories (DRAM) cells and integrated circuits which combine such cells with high performance logic circuit transistors on the same semiconductor chip.
2. Description of the Prior Art
Both improved performance and increased manufacturing economy can potentially be achieved by increasing integration density of elements (e.g. transistors, capacitors and the like) of integrated circuits as well as, in most cases, reduction of the size of those elements and the circuits they comprise. Therefore, there are currently substantial pressures to decrease both size and spacing of integrated circuit structures.
At least one lithographic process is generally required to establish the size and location of some of the elements on an integrated circuit chip and at any given time, several lithographic feature size regimes are in use or under development to establish processes which will provide economically acceptable manufacturing yields for a given application or market. For example, a half-micron minimum lithographic feature size may be the standard for products intended for the general public while a quarter-micron regime may be the standard for high-performance products which command a premium price and a sub-one-tenth-micron minimum feature size regime, sometimes referred to as a sub-100 nm regime may be under development to increase manufacturing yield while producing some amount of product for extremely demanding state-of-the-art applications where the need for performance that can not be otherwise obtained can offset costs of a relatively low manufacturing yield.
It should be understood that some designs for elements and circuits can be scaled from a given feature size regime to a smaller feature size regime while others cannot. For those that can be scaled in such a manner, it is customary to refer to the area of a given type of circuit or design by the number of minimum feature size areas, F
2
(F being the effective resolution of the system or the minimum feature dimension that can be resolved in a lithographic exposure), it requires. For example, modern DRAM cell designs generally require a minimum area of 6 to 12 F
2
on a chip, assuming that processes exist to carry out the fabrication of the design for a given F. At the same time, it should be recognized as a goal for a given F to be able to design and economically fabricate a given type of circuit in the same minimum number of F
2
areas required for a circuit having the same function at a larger minimum feature size or value of F, particularly where a given circuit design cannot be directly scaled.
At the same time, however, new structures are being developed to reduce the minimum area required for a given type of circuit. For example, to reduce a DRAM cell area from about 12F
2
to 6F
2
, the transistor gates (there being one transistor and one capacitor per cell in current designs and DRAM cells generally being produced at extremely high density) must be spaced apart by less than 2F and generally by only 1F. Due to such short distances, mask alignment cannot be used to form a contact between gates. Therefore, recently developed so-called borderless contacts are generally employed to make a contact between the gates. In general, borderless contacts exploit differential etch rate techniques in an area that overlaps two materials (often SiO
2
and SiN) in order to form a sub-lithographic size structure extending orthogonally to the chip surface.
Another new structure that enables a small DRAM cell size is a non-planar (vertical) access transistor. In this structure, the access transistor is formed on the walls of a trench or pillar. Such a transistor can have a gate length larger than 1F while maintaining a small wafer surface footprint. Therefore, the cell size scaling is effectively decoupled from the transistor channel length. This feature is important because of the existence of a lower channel length limit imposed by the charge retention requirement of memory cells in the array.
In DRAM circuits the retention of the stored charge can be affected by transistor leakage and capacitor size. That is, as capacitor size is reduced, the amount of stored charge representing stored data is correspondingly reduced and leakage through the transistor when the off-resistance is reduced may corrupt data unless refresh rates are increased; increasing, for example, the power consumption.
Non-planar transistors and borderless contacts are often combined in the same cell for greater density and charge retention characteristics in memory designs currently of interest. However, developing transistors at such small sizes and spacings and the use of techniques and structures such as borderless contacts and non-planar transistors generally precludes the development of other structures that may be important to transistor switching performance even though reduced transistor performance may be tolerable in some applications.
High performance logic transistors exhibit very high switching speed. Several techniques have been developed for increasing their performance but many be incompatible with high density memory structures described above. In order to achieve a very fast switching speed, logic transistors (e.g. transistors used in logic switching applications, as distinguished from isolation-type access transistors such as is employed in DRAM arrays) have a very thin gate dielectric, a heavily doped dual work function gate, carefully engineered source and drain impurity implantation profiles and a sub-lithographic (typically about 0.7-0.5F) trimmed gate.
Even with currently known designs which can be fabricated at sub-100 nm feature sizes, array transistors and logic transistors have much different fabrication requirements which have been considered as incompatible at least to the extent of requiring compromise of performance and/or operating margins to form both types of transistors on a single chip, if possible at all. Specifically, borderless contacts of array transistors require a thick insulator (generally nitride) while similar insulating materials are used as sidewalls only for controlling extension and possibly halo implants and the like. Similarly, array transistors and logic transistors require different sheet resistance of their gates. In the array, where there are long word lines, the gate sheet resistances should be minimized by creating a highly conductive metal layer on top of the gate electrode. On the other hand, relatively short logic gates use a silicide layer as their gate conductors. Further, the silicidation process results in a low source and drain contact resistance which is necessary in logic transistors to increase their switching speed.
Another area of incompatibility between array and logic transistor designs is spacer geometry even though spacers for array and logic transistors may be of the same material. Logic transistors imply spacers at the sides of the gates to control the location of implant and/or halo implants which control short channel effects and to separate the extension/halo implants from the source/drain implants (which are generally of different energy, energy spread and concentration). A single spacer thickness may suffice for NMOS transistors which use an impurity with relatively low diffusivity at high temperatures (e.g. arsenic) which limits the diffusion rate during subsequent heat treatment. However, to obtain desired dopant concentration profiles in PMOS transistors which employ an impurity with relatively high diffusivity at high temperatures (e.g. boron) and higher diffusion rates, at least two spacers, often of differing thickness, are generally required. Even more spacers may be necessary for both NMOS and PMOS transistors, depending upon desired electrical chartacteristics. On the other hand, as alluded to above, for array transistors located with a 1F separation, a total sidewall spacer thickness well belo

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