High performance gain cell architecture

Details High performance gain cell architecture High performance gain cell architecture

2005-01-18

2005-01-18

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S156000

Reexamination Certificate

active

06845059

ABSTRACT:
A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle. By extending the operation of the latch to accept data either from the sense amplifier, or from the memory data inputs, modified by the column address and masking bits, it is also possible to pipeline the read-out and the modify-write-back phases of a write cycle, allowing them to occur simultaneously. The architecture preferably employs a nondestructive read memory cell such as 2T or 3T gain cells, achieving an SRAM-like cycle and access times with a smaller and more SER immune memory cell.

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patent: 6005795 (1999-12-01), Hawkins et al.
patent: 6016268 (2000-01-01), Worley
patent: 6262912 (2001-07-01), Sywyk et al.
patent: 6614696 (2003-09-01), Kanno et al.

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