High performance DRAM structure employing multiple thickness gat

Details High performance DRAM structure employing multiple thickness gat High performance DRAM structure employing multiple thickness gat

1998-05-26

1999-12-28

Yoo, Do-Hyun

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365 51, 365 63, 365226, 36523006, G11C 700

Patent

active

060090235

ABSTRACT:
A DRAM device having improved performance of peripheral circuitry is described. The performance is improved by selectively having MOS transistors with a thinner gate oxide in peripheral circuits having a lower voltage applied to their gate electrodes. The DRAM device will maintain reliability by having MOS transistors with a thicker gate oxide in the memory cells and selected peripheral circuitry that are subjected to a higher voltage at their gate electrodes. Further this invention describes methods of fabricating the DRAM device with selectively placed multiple gate oxide thickness.

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