High performance DRAM and method of manufacture

Details High performance DRAM and method of manufacture High performance DRAM and method of manufacture

2000-05-10

2001-05-22

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S210000

Reexamination Certificate

active

06235574

ABSTRACT:

FIELD OF INVENTION
This invention relates to a dynamic random access memory (DRAM), and more particularly, to a DRAM in which the complementary transistors in the support circuitry have dual work-function gates.
BACKGROUND OF THE INVENTION
Presently a state-of-the-art DRAM comprises a silicon chip in whose central (array) area is disposed an array of memory cells that are arranged in rows and columns and in whose peripheral area is disposed the support circuitry for reading in and reading out binary digits (bits) stored in the memory cells. Generally at the present state of the art, each memory cell includes an N-channel metal-oxide-semiconductor field effect transistor (N-MOSFET) and the support circuitry includes both N-MOSFETs and P-channel metal-oxide-semiconductor field effect transistors (P-MOSFETs) which are commonly known as complementary metal-oxide semiconductor field effect transistors (C-MOSFETs). In most state-of-the-art DRAMs, both the array transistors and the support transistors use polycide (such as WSi
X
) gates that are formed as stacks that are essentially identical for all transistors. This approach is cost-effective since it permits all gates to be deposited and patterned simultaneously, ensuring ease and reduced cost of manufacture. Typically the stacks are sequential layers of n-type doped polysilicon, a polycide, and a silicon nitride cap. This however poses limitations on the DRAM performance, particularly with respect to the P-MOSFET in the support circuitry. This will become more serious in the future when enhanced performance of the support circuitry will be necessary to cope with the improved performance requirements that will then be needed.
Also, DRAM technology typically aims to reduce the cell size in the arrays to permit higher density and increased productivity. One of the most effective ways to reduce the array cell size is to use borderless contacts to the source/drain regions (the output of the transistor typically coupled to a bit line of the DRAM) of the transistors of the memory cell. This requires a relatively thick SiN cap on top of the electrically conducting portion of the gate stack. Such a cap, which is also needed in the support circuitry, adds difficulty to line width control during etching, which in turn makes difficult control of gate width, another important factor in device performance.
High performance logic circuits, on the other hand, typically are now manufactured with n-type and p-type doped polysilicon as part of the gate stack for N-MOSFETs and P-MOSFETs, respectively, which is generally described as a dual work-function stack. These are manufactured with so-called salicide (self-aligned suicide) processes that simultaneously dope the gate polysilicon as well as the silicon substrate to form the source and drain diffusion regions. The absence of the need of the SiN cap in this approach results in better line-width control. The disadvantage to this approach is the need for additional masks. This increases the process complexity as well as a reduction in the allowed thermal budget because of the large thermal diffusion constant of the p-type dopant (typically boron). This factor limits the use of the anneal steps generally used to reflow the customary borophospho-silicate glasses (BPSG) because of the high aspect ratio of the spaces between gates in the circuitry.
SUMMARY OF THE INVENTION
In one aspect the present invention is directed to a method for manufacturing high-performance DRAMs using conventional technology in a novel fashion to provide dual work-function gates for C-MOSFETs transistors of the support circuitry so that improved performance becomes possible for the support circuitry. In particular, the novel process advantageously involves use in the support circuitry of the salicide gate approach common in the CMOS-technology generally now limited to use for high-speed low power logic circuitry.
In particular, the process flow involved is one that does not compromise the ground rules applicable to the array transistors of the individual cells, but does provide for the desired dual work-function gates in the CMOS support circuitry transistors and involves a thermal budget that is consistent with high electrical performance of the final product.
More particularly, the method of the present invention effectively decouples the patterning and gap-filling steps in the manufacture of the array transistors from these steps in the manufacture of support circuitry transistors by the initial inclusion of an etch stop layer, for example of silicon oxide, in the multilayer stack used to form the support circuitry transistors. In addition, a polycide layer is part of the gate stack only of the array transistors and so the support circuitry transistors can be readily made using conventional salicide techniques. Finally, the process steps are arranged such that the thermal budget is significant in the manufacture only of the array transistors where the type dopants for which the thermal budget is critical have not yet been introduced into the silicon chip. Additionally, the process permits the spaces between the support circuitry gates to have a reduced aspect ratio so that they can be filled at lower temperatures than would otherwise be the case.
Accordingly, the invention may be viewed broadly as a process for preparing a DRAM in a semiconductor body, such as a silicon chip, in which the memory cells are arrayed in the central area of the chip and the support circuitry is formed in its peripheral area. As is characteristic of state-of-the art DRAMs, the memory cell transistors are all N-MOSFETs and support circuitry includes both N-MOSFETs and P-MOSFETs. An important feature is that each of the array N-MOSFETS includes an N-doped polycide gate contact and each of the MOSFETs of the support circuitry includes appropriately doped polysilicon gates. A related feature is that source, drain and gate contacts of the support circuitry transistors are all formed by a self-aligned technique that results in borderless salicide contacts.
Viewed from an apparatus aspect, the present invention is directed to a DRAM that comprises a silicon chip in whose central area are formed an array of memory cells each including an N-MOSFET and in whose peripheral area are formed the support circuitry including both N-MOSFETs and P-MOSFETs characterized in that the N-MOSFETs in the memory cells use N-doped polycide gates, the N-MOSFETs in the support circuitry use N-doped polysilicon gates and the P-MOSFETs in the support circuitry use P-doped polysilicon gates.
Viewed from a method aspect, the present invention is directed to a method for forming a DRAM that comprises a silicon chip in which the central area of the chip includes arrays of memory cells that use N-MOSFETs and the peripheral area of the chip includes support circuitry that uses C-MOSFETs. The method comprises the steps of: forming over the surface of the chip area a masking layer of silicon oxide and removing the layer selectively from the central portion where the memory cell arrays are to be included, but leaving it in place in the peripheral portion where the support circuitry is to be included; forming the N-MOSFETs of the memory cells in the central area and including in such N-MOSFETs gate conductors that include an underlying polysilicon layer that is doped with donor atoms and an overlying layer that is a metal silicide; covering the chip area with a masking layer and removing the masking layer selectively from the central area of the chip; removing said silicon oxide layer from the peripheral portion of the chip area; covering said peripheral portion with a masking layer and removing it where N-MOSFETs are to be formed; forming the N-MOSFETs of the support circuitry in the peripheral portion and including in such N-MOSFETs gate conductors that include an underlying polysilicon layer that is doped with donor atoms and an overlying layer that is a metal suicide; covering the peripheral area with a masking layer and removing it where P-MOSFETs are to be formed; and forming the

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