High performance cost optimized memory with delayed memory write

Details High performance cost optimized memory with delayed memory write High performance cost optimized memory with delayed memory write

1998-10-09

2000-06-13

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Signals

365194, 365233, G11C 700

Patent

active

060757302

ABSTRACT:
A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.

REFERENCES:
patent: 5566108 (1996-10-01), Kitamura
patent: 5724287 (1998-03-01), Takenada
patent: 5748542 (1998-05-01), Zheng et al.
patent: 5751644 (1998-05-01), Ansel et al.
patent: 5761150 (1998-06-01), Yukutake et al.
patent: 5886948 (1999-03-01), Ryan

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