High performance CMOS device structure with mid-gap metal gate

Details High performance CMOS device structure with mid-gap metal gate High performance CMOS device structure with mid-gap metal gate

2002-04-19

2004-07-13

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C257S392000, C257S376000, C257S402000, C257S204000, C257S069000, C257S327000, C257S332000, C438S217000, C438S300000, C438S197000, C438S301000, C438S303000

Reexamination Certificate

active

06762469

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to high performance CMOS device structures with a mid-gap metal gate, and more particularly pertains to high performance CMOS device structures with a mid-gap work function metal gate wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (~500 mV), as are required by CMOS devices with a mid-gap metal gate.
2. Discussion of the Prior Art
The problems and issues associated with the design of CMOS devices with a mid-gap work function metal gate are well known and recognized in the prior art (e.g. E. Josse and T. Skotnicki, IEDM 1999).
In the fabrication of high performance CMOS devices with ultra-thin gate dielectrics and polysilicon gates, the depletion layer formed in the polysilicon gate in inversion bias becomes a significant fraction of the gate capacitance and degrades the device performance.
The use of a metal gate in these CMOS devices alleviates this problem. Two different metals with appropriate workfunctions can be used, a first metal with a first workfuction for the PFET area and a second metal with a second workfunction for the NFET area. However, this approach adds significant cost and complexity to the process. Alternatively, the same metal can be used for the gate of both the PFET area and NFET area with a mid-gap workfunction. For CMOS mid-gap workfunction metal gates, the threshold voltage Vt for both the PFET area and the NFET area become unacceptably high. The threshold voltage has to be adjusted downwardly by adding p-type dopant to the surface of the PFET area and n-type dopant to the surface of the NEFT area.
SUMMARY OF THE INVENTION
The present invention provides high performance (surface channel) CMOS devices with a mid-gap work function metal gate, and is applicable to 0.1 um technology structures. Pursuant to the present invention, an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (~500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ boron (B) doped epitaxial layer or a B and carbon (C) co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The present invention produces B diffusion profiles in an epitaxial layer of B doped silicon or B and C co-doped silicon on the PFET area of the CMOS devices. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.
A further object of the subject invention is the provision of a method of fabricating mid-gap metal gate CMOS devices with good short channel effects wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (~500 mV), as are required by CMOS devices with a mid-gap metal gate.


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