Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-11-04
1998-06-09
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438305, H01L 21336
Patent
active
057633118
ABSTRACT:
A method of fabricating a high performance asymmetrical field effect transistor (FET) includes the steps of forming a gate oxide and a gate electrode on a layer of semiconductor material of a first conductivity type. The gate electrode includes a first side edge adjacent a first region of the semiconductor material and a second side edge proximate a second region of the semiconductor material. First and second lightly doped regions are formed in regions of the semiconductor material not covered by the gate oxide, and extending away from the first and second side edges of the gate electrode, respectively. First and second sidewall spacers are formed proximate the first and second side edges of the gate electrode, respectively, each sidewall spacer including a composite sidewall spacer of a first and a second spacer material. Lastly, a very highly doped source region and a highly doped drain region are formed in the first and second regions, respectively, the very highly doped source region having a greater dopant concentration of the second conductivity type than the highly doped drain region and the highly doped drain region having a dopant concentration greater than the lightly doped region extending away from the second side edge of said gate electrode. A novel FET is disclosed also.
REFERENCES:
patent: 5171700 (1992-12-01), Zamanian
patent: 5286664 (1994-02-01), Horiuchi
patent: 5510279 (1996-04-01), Chien et al.
patent: 5578509 (1996-11-01), Fujita
Gardner Mark I.
Hause Fred
Kadosh Daniel
Advanced Micro Devices , Inc.
Balconi-Lamica Esq. Michael J.
Chaudhari Chandra
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