High noise-margin TTL buffer circuit capable of operation with w

Details High noise-margin TTL buffer circuit capable of operation with w High noise-margin TTL buffer circuit capable of operation with w

1995-03-22

1997-03-18

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Logic level shifting

326 73, H03K 190185

Patent

active

056126352

ABSTRACT:
A buffer circuit for converting logic signals generated by apparatus implemented in a TTL technology to logic signals processed by apparatus implemented by the CMOS technology includes an input stage (10, 11, 12, 13, 17), a voltage-control (14, 15) stage for causing the buffer circuit to vary the input voltage level required to switch the state of the buffer circuit output signal, and a hysteresis stage (16) for causing the switching of the output signal level to be different for the rising and falling edges of the input signal. The voltage-control stage (14, 15) provides a improvement in the noise margin of both the VTTL(High) switching level and the VTTL(Low) switching level.

REFERENCES:
patent: 4216390 (1980-08-01), Stewart
patent: 5036226 (1991-07-01), Tonnu et al.
patent: 5276366 (1994-01-01), Quigley et al.

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