High mobility FETS using A1203 as a gate oxide

Details High mobility FETS using A1203 as a gate oxide High mobility FETS using A1203 as a gate oxide

2001-06-25

2003-01-28

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S785000, C438S591000, C438S624000

Reexamination Certificate

active

06511876

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a method of forming a dielectric material for use in an electronic semiconductor device such as a field effect transistor (FET). Additionally, the method of the present invention can also be used in forming a capacitor.
BACKGROUND OF THE INVENTION
In the semiconductor industry, dielectric materials in high-density circuits appear as capacitors in dynamic random access memory (DRAM) applications, gate dielectrics in transistors and as decoupling capacitors. The dielectric materials in these structures are typically silicon dioxide, SiO
2
, which has a dielectric constant of about 4.0. As today's generation of circuits become smaller and smaller, the dielectric materials employed therein must be made thinner to satisfy circuit requirements.
The use of thin, low dielectric constant materials in today's generation of circuits is undesirable since such materials lead to leaky circuits and therefore large power consumption. Thus, it would be beneficial if the dielectric constant of the dielectric material used in such circuits could be increased. By increasing the dielectric constant, thicker oxides with a lower leakage current could be obtained which are electrically equivalent to thinner SiO
2
.
In semiconductor field effect transistor devices, for example, SiO
2
gate oxide leakage currents are rapidly increasing as device dimension are shrinking. For devices containing a gate length of about 100 nm or less, SiO
2
may not be able to be used for future microprocessors and memory chips.
Most of the current research is in developing high dielectric constant, i.e., high-k, dielectrics that are based upon binary metal oxides and silicates; See, for example, G. D. Wilk, et al., J. Appl. Phys., 89 (2001), page 5243 and other references cited therein. Recently, it has been demonstrated that Al
2
O
3
NFETs (k=10) with an effective channel length, 1
eff
, of 0.08 &mgr;m, show more than 100×reduction in leakage currents and equal or better reliability than SiO
2
at room temperature. The foregoing results have been published by D. A. Buchanan, et al., IEDM Technical Digest (2000), page 223. A standard polysilicon, i.e., poly Si, FET process was employed in the Buchanan, et al. article except that Al
2
O
3
was employed as the gate dielectric instead of SiO
2
. Generally, in such a process, cooling of the substrate occurs prior to formation of the binary metal oxide thereon.
One main problem with the prior art approach mentioned above is that the devices, i.e., NFETs, containing Al
2
O
3
as a gate dielectric show a much-reduced mobility (a 5×reduction) as compared to SiO
2
. The term “mobility” as used herein denotes the ability of electrons or holes in the semiconductor to move from one end of the channel to the other end. High channel mobility using a given gate dielectric material is important in the semiconductor industry. High channel mobility and therefore faster switching speeds are achieved by reducing trapped charge in the gate stack region. Reduced trapped charge leads to a device which does not exhibit hysteresis in the capacitance-voltage curve. Such a hysteric behavior in the capacitance-voltage curve is shown, for example, in FIG.
1
.
In view of the above drawbacks mentioned with prior art high-k dielectrics, there is a continued need for developing a new and improved method of forming a high-k dielectric on the surface of a substrate wherein the mobility of charge carriers within the channel is significantly increased as compared with high-k dielectrics that are prepared by conventional processes.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a high-k dielectric material.
Another object of the present invention is to provide a high-k dielectric material which exhibits low leakage current that is on the order of about 1 A/cm
2
or less at its operating potential.
A further object of the present invention is to provide a high-k dielectric material which provides an increased mobility by reducing trapped charge or moving said charge away from the underlying semiconductor substrate.
A yet further object of the present invention is to provide a high-k dielectric film that is made using processing steps that are compatible with existing complementary metal oxide semiconductor (CMOS) processing steps.
These and other objects and advantages are obtained in the present invention by providing a method wherein the wafer is kept at elevated temperatures (of about 250° C. or above) during the entire process. That is, during the various processing steps of the present invention, especially during the transfer from one reactor chamber to another, the wafer is not allowed to cool to room temperature. By maintaining the temperature of the wafer at about 250° C. or above, a large improvement in electrical characteristics, particularly the mobility, is observed. While not be bound by any theory, it is believed that by not allowing the wafer to cool, a cleaner process with less contaminants is obtained.
Specifically, the inventive method of the present invention comprises the steps of:
(a) placing a substrate in a first reactor chamber;
(b) forming an interfacial dielectric layer on an upper surface of said substrate at a temperature of about 300° C. or above;
(c) transferring said substrate from said first reactor chamber to a second reactor chamber in a controlled gaseous ambient or vacuum, while maintaining said substrate at a temperature of about 300° C. or above; and
(d) forming a high-k dielectric material atop said interfacial dielectric layer.
In accordance with the present invention, the substrate may optionally be transferred to another reactor chamber wherein a gate contact is formed atop the high-k dielectric material. When such a transferring step is employed, the substrate including the high-k dielectric material may also be maintained at a temperature of about 300° C. or above. In another embodiment of the present invention, the substrate is cooled after deposition of the high-k dielectric material, and the gate contact is formed in a separate system.
It is noted that the term high-k dielectric material includes any dielectric material that has a dielectric constant that is higher than SiO
2
. Examples of such high-k dielectric materials include, but are not limited to: metal oxides such as Al
2
O
3
, ZrO
2
, HfO
2
, or Ta
2
O
5
; perovskite-type oxides; metal silicates; metal nitrides; and any combination or multilayer thereof. In a preferred embodiment, the high-k dielectric is a metal oxide, with Al
2
O
3
being one preferred metal oxide.


REFERENCES:
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patent: 5998236 (1999-12-01), Roeder et al.
patent: 6218260 (2001-04-01), Lee et al.
patent: 6319766 (2001-11-01), Bakli et al.
patent: 6426308 (2002-07-01), Park et al.
patent: 2002/0052124 (2002-05-01), Raaijmakers et al.
patent: 2002/0115252 (2002-08-01), Haukka et al.
Science-and-Technology-of-Advanced-Materials (UK), vol. 1.No.3, p. 187-90., Published: Elsevier.*
G.D. Wilk, R.M. Wallace, J.M.Anthony, May 15, 2001, Applied Physics Review, vol. 89, p. 5243.

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