High-K tunneling dielectric for read only memory device and...

Details High-K tunneling dielectric for read only memory device and... High-K tunneling dielectric for read only memory device and...

2002-12-24

2004-09-28

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S267000, C438S279000

Reexamination Certificate

active

06797567

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a structure of an integrated circuit (IC) and a fabrication method thereof. More particularly, the present invention relates to a read only memory device that comprises a high dielectric constant (high-K) tunneling dielectric layer and a fabrication method thereof.
2. Description of Related Art
With the advances in miniature processing technology in a semiconductor manufacturing process, the miniaturization of a device dimension provides an increase of integration of semiconductor device, an enhancement of the function of integrated circuit, a lowering of cost, an improvement of the devices replacement rate and a lowering of the devices consumption rate. Accompany with the reduction of the dimension of a semiconductor device, the thickness of the dielectric layer (oxide layer) between the gate and the substrate needs to become thinner in order to maintain the capacitance between the gate and the channel.
For a programmable and erasable read only memory device, silicon dioxide formed by thermal oxidation is typically used to form the tunnel oxide layer. Therefore, as the device dimension for a read only memory device continues to reduce, the thickness for the tunnel oxide layer must become thinner accordingly. However, the tunnel oxide layer comprises a low limit in thickness. In other words, the tunnel oxide layer must comprise a certain thickness. When the thickness of the tunnel oxide layer is below the lower limit, many problems will surface. For example, during a subsequent thermal process, a thin tunnel oxide layer cannot prevent oxygen or dopants to diffuse into the substrate or to be trapped in the tunnel oxide layer, thereby changing the devices threshold voltage. Further, when the thickness of the tunnel oxide layer is smaller than the lower limit, the retention property of the tunnel oxide layer will become inferior. Consequently, the electrons that are stored in the charge trapping layer will flow into the substrate through the tunnel oxide layer. Losing the stored information and generation of current leakage are thereby resulted. Therefore, as indicated in the above, limited by the thickness of the tunnel oxide layer, the read only memory device dimension cannot be reduced further.
SUMMARY OF INVENTION
Accordingly, the present invention provides a read only memory device with a high-K tunneling dielectric layer and a fabrication method thereof, wherein oxygen or dopants being diffused into the substrate or trapped in the tunneling dielectric layer to adversely affect the threshold voltage is prevented.
The present invention also provides a read only memory device with a high-K tunneling dielectric layer and a fabrication method thereof, wherein the electrons that are stored in the charge trapping layer is prevented from leaking into the substrate. As a result, loss of the stored information and current leakage are prevented.
The present invention also provides a read only memory device that comprises a high-K tunneling dielectric layer and a fabrication method thereof, wherein oxidation reaction to generate silicon dioxide at the interface between the tunneling dielectric layer and the substrate or between the tunneling dielectric layer and the electron trapping layer is prevented.
The present invention further provides a read only memory device with a high-K tunneling dielectric layer and a fabrication method thereof, wherein the tunneling dielectric layer comprises a lower interfacial trap density to prevent oxygen, dopants or electrons being trapped at interface between the tunneling dielectric layer and the electron trapping layer or between the tunneling dielectric layer and the substrate.
The present invention also provides a read only memory device with a high-K tunneling dielectric layer and a fabrication method thereof, wherein the fabrication method is compatible with the present manufacturing process.
The present invention further provides a read only memory device that comprises a high-K tunneling dielectric layer and a fabrication method thereof, wherein a lower operating voltage can use to operate the device.
The present invention further provides a read only memory device that comprises a high-K tunneling dielectric layer and a fabrication method thereof, wherein the read only memory device can be further reduced in dimension.
The present invention provides a fabrication method for a read only memory device that comprises a high-K tunneling dielectric layer, wherein the tunneling dielectric layer is formed over the substrate. A material for forming the tunneling dielectric layer is selected from the group consisting of hafnium oxynitride (H
f
O
x
N
y
) and hafnium silicon oxynitride (H
f
SiON). Thereafter, an electron trapping layer and a top oxide layer are sequentially formed over the tunneling dielectric layer. The top oxide layer, the electron trapping layer and the tunneling dielectric layer are then patterned to form a plurality of stacked structures. A doped region is then formed in the substrate between the stacked structures. Thereafter, a buried drain oxide layer is formed over the surface of the doped region, followed by forming a patterned conductive layer over the substrate as the word line of the read-only memory device.
The present invention provides a read only memory device with a high-K tunneling dielectric layer, wherein the read only memory device comprises at least a substrate, a tunneling dielectric layer, an electron trapping layer, a top oxide layer, a conductive layer and a buried drain region. The tunneling dielectric layer is disposed over the substrate and this tunneling dielectric layer is formed with a material selected from the group consisting of (H
f
O
x
N
y
) and (H
f
SiON). The electron trapping layer is disposed over the tunneling dielectric layer, and the top oxide layer is positioned over the electron trapping layer, wherein the tunneling dielectric layer, the electron trapping layer and the top oxide layer form a stacked structure. The conductive layer is disposed at least over the top oxide layer, and the buried drain region is configured in the substrate beside both sides of the stacked structure.
Accordingly, the present invention replaces the conventional silicon oxide with (H
f
O
x
N
y
) or (H
f
SiON) as the tunneling dielectric layer of the read only memory device. Since the tunneling dielectric layer of the present invention is thicker than that of a conventional silicon dioxide layer, the thickness of the tunneling dielectric layer formed according to the present invention is thus sufficient to prevent the penetration of oxygen, dopants and/or electrons through the tunneling dielectric layer into the substrate.
Additionally, since the aforementioned tunneling dielectric layer comprises nitrogen, the tunneling dielectric layer thereby has a denser structure. Beside being able to prevent the penetration of oxygen, dopants or electrons through the tunneling dielectric layer into the substrate, the trapping of oxygen, dopants or electrons in the tunneling dielectric layer is also prevented.
In addition to resolving the aforementioned problems, the application of (H
f
O
x
N
y
) or (H
f
SiON) as the tunneling dielectric layer of a read only memory device can also provides the following advantages.
Since the tunneling dielectric layer comprises nitrogen therein, oxidation reaction to generate silicon dioxide at the interface between tunneling dielectric layer and the substrate or the electron trapping layer is prevented.
Further, since a material for forming the tunneling dielectric layer comprises a lower interfacial trap density, oxygen, dopants or electrons will not be trapped at the interface between the tunneling dielectric layer and the electron trapping layer or between the tunneling dielectric layer and the substrate. The stability of the devices threshold voltage can be increased.
Further, the tunneling dielectric layer can maintain a good contact with the polysilicon material at high temperature. Therefore, even after the

Affiliated with

Also associated with

Rating

High-K tunneling dielectric for read only memory device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High-K tunneling dielectric for read only memory device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-K tunneling dielectric for read only memory device and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3270053