High K gate electrode

Details High K gate electrode High K gate electrode

1997-12-18

2001-07-10

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S411000, C438S216000, C438S591000

Reexamination Certificate

active

06258675

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuit manufacturing and more particularly to a gate electrode having a high K value.
BACKGROUND OF THE INVENTION
An insulated-gated field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located within a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and the drain are formed by introducing dopants of a second conductivity type (P or N) into a semiconductor substrate of a first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also known as polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anistropically etched to provide a gate that provides a mask during formation of the source and drain by ion implantation. Thereafter, a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3 volts), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For example, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator, causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device. Hot carrier effects are also referred to as “bridging.”
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). An LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to the gate on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity heavily doped region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is further away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affect the device characteristics. The lightly doped region is not necessary for the source—unless bidirectional current is used—however, lightly doped regions are typically formed for both the source and the drain to avoid additional processing steps.
The formation of spacers to ultimately create lightly doped regions, however, is disadvantageous in that it requires extra processing steps that may add cost, complexity and time to the formation of a transistor. In the process just described, for example, two extra processing steps are required: the formation of spacers, and the application of a second ion implantation. Thus, there is a need for the formation of transistors that either do not require lightly doped regions, but that have the same performance characteristics as lightly doped regions, or that provide for the formation of lightly doped regions in less than two ion implantations.
SUMMARY OF THE INVENTION
The above-mentioned shortcomings, disadvantages and problems are addressed by the present invention, which will be understood by reading and studying the following specification. The invention relates to a gate electrode having a high K value. In one embodiment, a method includes three steps. In the first step, a gate electrode layer is formed on a substrate. The gate electrode layer includes at least one layer, this layer having a high K value. In the second step, a gate is formed on the gate electrode layer. The gate masks a portion of the gate electrode layer. In the third step, the gate electrode layer is removed, except for the portion masked by the gate.
Because the gate is “stacked” on the gate electrode layer, the device formed pursuant to this embodiment of the invention is not susceptible to bridging and other hot carrier effects as are typical prior art devices that do not have lightly doped regions. That is, the raising of the gate height-wise vis-a-vis the top surface of the substrate in which source and drain regions are to be formed ensures that bridging will not occur, militating against the need for lightly doped regions. This is an advantage of the invention.
In a further embodiment of the invention, the side and top edges of the gate are oxidized and removed, decreasing the length of the gate. This decrease in the length of the gate further serves to prevent bridging and other hot carrier effects, by increasing the lateral distance between the gate and the source and drain regions. This is a further advantage of the invention.
The present invention describes methods, devices, and computerized systems of varying scope. In addition to the aspects and advantages of the present invention described here, further aspects and advantages of the invention will become apparent by reference to the drawings and by reading the detailed description that follows.


REFERENCES:
patent: 4777517 (1988-10-01), Onodera et al.
patent: 4791471 (1988-12-01), Onodera et al.
patent: 4889817 (1989-12-01), Saito et al.
patent: 4905061 (1990-02-01), Ohmuro et al.
patent: 5183771 (1993-02-01), Mitsui et al.
patent: 5225286 (1993-07-01), Fujikawa et al.
patent: 5243202 (1993-09-01), Mori et al.
patent: 5286994 (1994-02-01), Ozawa et al.
patent: 5292673 (1994-03-01), Shinriki et al.
patent: 5319229 (1994-06-01), Shimoji et al.
patent: 5528068 (1996-06-01), Ohmi
patent: 5596214 (1997-01-01), Endo
patent: 5619051 (1997-04-01), Endo
patent: 5688724 (1997-11-01), Yoon et al.
patent: 5866473 (1999-02-01), Xiang et al.
patent: 5880508 (1999-03-01), Wu
patent: 5891798 (1999-04-01), Doyle et al.
patent: 51-138950 (1978-06-01), None
patent: 53-062987 (1978-06-01), None
patent: 03162754 (1993-01-01), None
patent: 05013756 (1993-01-01), None
IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972.

Affiliated with

Also associated with

Rating

High K gate electrode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High K gate electrode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High K gate electrode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2477345