High-K gate dielectric process with process with self...

Details High-K gate dielectric process with process with self... High-K gate dielectric process with process with self...

1999-05-03

2002-12-10

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S596000, C438S598000, C438S618000, C257S410000, C257S411000

Reexamination Certificate

active

06492249

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with self aligned contacts.
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin or shallow extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects are among the most important scaling issues for mainstream CMOS technology and can cause threshold voltage roll-off and drain-inducted barrier lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques.
Conventional ion implantation and diffusion doping techniques make transistors on the IC susceptible to short-channeling effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically in to the bulk semiconductor substrate.
As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), CMOS fabrication processes have considered a two-dimensional channel-doping technique. A two-dimensional doping implant can form a channel-doping profile in the lateral direction that is non-uniform and a channel-doping profile in the vertical direction that is a super-steep retrograded channel-doping profile. The two-dimensional channel-doping profile is critical to scaling (i.e., proportional operation and structural elements in the ultra-small dimensions of a sophisticated transistor).
The two-dimensional channel doping profile is conventionally formed with deep pocket implants which surround the entire source and the entire drain. The implants have an opposite conductivity type to that of the source and drain and form a “halo-like” structure around the border of the source and drain. The halo-like structure increases the doping concentration near the junction of the source and drain. Increased doping concentration near the junction of source and drain degrades (i.e., increases) the source/drain junction capacitance (e.g., parasitic capacitance). Increased parasitic capacitance reduces the speed of the transistor.
Thus, shallow extensions and deep pocket implants are utilized to alleviate short channel effects. However, the formation of shallow extensions is difficult as transistors become smaller and pocket implants can adversely effect the speed of transistors when fabricated according to conventional processes.
Yet another major problem associated with CMOS scaling is related to conventional gate dielectric materials disposed under the gate conductor.
Generally, conventional gate dielectric materials, such as, silicon dioxide are less reliable as transistor size is decreased. For example, silicon dioxide is subject to high leakage current caused by “direct tunneling effect.” Generally, as channel lengths approach 70 nanometers (nm) or less, high dielectric constant (k) dielectric materials must replace silicon dioxide dielectric materials.
High k dielectric materials cannot be utilized in conventional CMOS processes due to the thermal instability associated with the molecular structure of high k dielectric materials. High temperature treatments, such as, source/drain implantation activation annealing (typically 1050° C. for 10 seconds) can cause reactions between the high k dielectric materials and silicon. Also, high k dielectric materials can change phases (amorphous to crystalline) in response to the high temperature treatments. For example, one high k dielectric material, tantalum pentaoxide (Ta
2
O
5
), changes phase from an amorphous material to a crystalline material at approximately 800° C. Crystalline Ta
2
O
5
material has a high leakage current.
Still another problem associated with CMOS scaling involves spacings between gate structures and contacts. Contacts are required in an IC device to provide electrical connections between layers or levels of the integrated circuit device. Semiconductor devices typically include a multitude of transistors which are coupled together in particular configurations through contacts.
Contacts are generally coupled to the source region and/or drain region of the transistors disposed on the integrated circuit. The contact is often connected to the source and drain region via a silicide layer. The silicide layer is generally formed in a high temperature process. The silicide layer reduces drain/source series resistance.
In conventional processes, contacts must be spaced from the gate conductor by a minimum acceptable distance (often at least one minimum lithographic feature). Contacts must be spaced apart from the gate structure so alignment errors do not result in a shorting or severe crosstalking or stacked gate with the source contact or the drain contact. As lithographic feature sizes are reduced according to advanced fabrication processes, the spacing between the contacts and the gate structure becomes even more critical because slight alignment errors can cause a short circuit. The spacing between the contact and gate contributes to the overall size of the transistor and hence, the size of the IC.
Thus, there is a need for a process which prevents misalignment between the contact and gate and allows the spacing between the contact and the gate to be reduced. Further, there is a need for a method of manufacturing an integrated circuit with a high-k gate dielectric layer and a low-k interlevel dielectric layer. Even further still, there is a need for transistor

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