Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-04-08
2003-12-09
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000, C438S216000, C438S286000, C438S479000
Reexamination Certificate
active
06660578
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a dielectric layer and an associated barrier layer for use with P-doped devices, such as P-type metal oxide semiconductors (PMOS).
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices (e.g., transistors, memory cells and so forth) having structural features that are as small as possible. Although the fabrication of smaller devices allows more devices to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects.
For example, metal oxide semiconductor field effect transistors (MOSFETs) are traditionally made with a gate dielectric layer for separating a gate electrode and a body region. The body region is formed in an active region of a layer of semiconductor material and is disposed between a source and a drain. The source and the drain are formed by implanting N-type or P-type impurities in the layer of semiconductor material. Although MOSFETs have successfully been used in the construction of a integrated circuits (e.g., complimentary metal oxide semiconductor (CMOS) integrated circuits), MOSFET reliability is susceptible to downscaling. For instance, gate dielectric breakdown and/or tunneling through the gate dielectric can occur in devices having a relatively thin gate dielectric (e.g., approaching about 10 Å) that is made from a traditional material (e.g., SiO
2
).
Accordingly, there exists a need in the art for improved dielectric layers for semiconductor devices as well as techniques and structures for protecting the improved dielectric layers during various device fabrication steps.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a semiconductor device configured as a MOSFET. The semiconductor device includes a body formed between a source and a drain in an active region of a layer of semiconductor material; a gate electrode having P-type doping formed on the layer of semiconductor material above the body and separated from the body by a gate dielectric made from a layer of high-K material; and a barrier layer disposed between the gate dielectric and the gate electrode, the barrier layer inhibiting ion penetration into the gate dielectric during doping of the gate electrode.
According to another aspect of the invention, the invention is directed to a semiconductor wafer. The wafer includes a first group of semiconductor devices each including: a first semiconductor component receiving P-type doping; a second semiconductor component; a first high-K dielectric layer separating the first semiconductor component and the second semiconductor component; and a barrier layer disposed between the high-K dielectric layer and the first semiconductor component for inhibiting P-type ion penetration into the high-K dielectric layer during the P-type doping of the first semiconductor component. The wafer further includes a second group of semiconductor devices each including: a third semiconductor component; a fourth semiconductor component; and a second high-K dielectric layer separating the third semiconductor component and the fourth semiconductor component. The first high-K dielectric layer for each of the semiconductor devices from the first group is made from the same layer of high-K material as used to make the second high-K dielectric layer for each of the semiconductor devices from the second group.
According to yet another aspect of the invention, the invention is directed to a method of fabricating a wafer having a section for P-type doped semiconductor devices. The method includes providing a layer of semiconductor material; forming a high-K dielectric material layer on the layer of semiconductor material; forming a layer of barrier material on the high-K dielectric material layer and patterning the layer of barrier material to be coextensive with the section for P-type doped semiconductors; forming a layer of material to receive P-type doping on at least the layer of barrier material; and implanting the layer of material to receive P-type doping with P-type dopant and wherein the layer of barrier material inhibits P-type ion penetration into the high-K dielectric material layer during implantation.
REFERENCES:
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patent: 6020024 (2000-02-01), Maiti et al.
patent: 6040207 (2000-03-01), Gardner et al.
patent: 6051865 (2000-04-01), Gardner et al.
patent: 6225168 (2001-05-01), Gardner et al.
patent: 6492217 (2002-12-01), Bai et al.
patent: 2003/0032251 (2003-02-01), Chen et al.
Karlsson Olov
Krivokapic Zoran
Wang HaiHong
Xiang Qi
Yu Bin
Coleman W. David
Lee Hsien-Ming
Renner , Otto, Boisselle & Sklar, LLP
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