High integrity vias

Details High integrity vias High integrity vias

1998-06-23

2000-08-01

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257758, H01L 2348, H01L 2352, H01L 2940

Patent

active

060970901

ABSTRACT:
Vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. Embodiments include depositing a dielectric interlayer and forming a misaligned through-hole therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

REFERENCES:
patent: 5619072 (1997-04-01), Mehta
patent: 5925932 (1999-07-01), Tran et al.

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