Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-23
2002-10-01
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S675000, C438S676000, C438S687000
Reexamination Certificate
active
06458694
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for forming interconnects (wiring), and more particularly to a method and apparatus for forming interconnects (wiring) on a substrate such as a semiconductor wafer by filling conductive materials such as copper (Cu) in fine recesses formed in a surface of the substrate in a predetermined interconnect pattern.
2. Description of the Related Art
Generally, aluminum or aluminum alloys have been used as a material for forming interconnects (wiring) for a semiconductor. However, in recent years, there has been a growing tendency to replace aluminum with copper for the following reasons: Copper has excessively low electric resistivity of 1.72 &mgr;&OHgr; cm which is about 40% lower than that of aluminum, and hence copper has the advantage of reduced RC delay phenomenon and has higher resistance against electromigration damage than aluminum. For example, even if current density increases up to 1×10
6
or 1M A/cm
2
or more due to a drastic reduction in a cross-sectional area of a line, there is little probability that electromigration occurs in the interior of the line. Further, copper is more suitable for dual damascene process than aluminum, and has a high capability that a complicated and fine structure of multi-level interconnections can be manufactured at a low cost.
In order to form fine wiring or interconnects with copper, since practical dry etching process of copper has not been established, it is inevitable to employ the so-called damascene process in which copper is filled into patterned trenches and vias preformed in insulating layers of a semiconductor substrate.
As a means for filling copper into the minute trenches or vias by the damascene process, there are various ways including CVD, sputter deposition (sputtering), electroplating, and the like. Among these processes, the sputter deposition which combines film deposition by sputtering and heating has the advantage of high deposition rate with excellent film quality. In addition, existing sputtering apparatuses and technology for depositing aluminum are still usable.
In the film deposition by sputtering (sputter deposition), a substrate and a target are disposed in confrontation with each other in a chamber, a high voltage is applied between the substrate and the target, and a sputtering gas is introduced into the chamber. Thus, high-energy particles such as ions of sputtering gas which have been ionized and accelerated collide with the target to cause particles of the target material to be sputtered and emitted from the target, and the emitted particles of the target material are deposited over the substrate to thus fill the target material into the minute trenches or vias for thereby forming patterned interconnects.
However, this sputtering process is problematic for its poor step coverage characteristic, i.e., capability of covering portions having difference in level, is low, because sputtered atoms travel straight.
FIG. 10
is a schematic view showing the state of an overhang of copper formed at an inlet portion of a fine recess after copper as a metalizing material is deposited to fill the fine recess for preparing interconnects.
As shown in
FIG. 10
, when copper as a wiring material is filled by the sputter deposition process in a fine recess
102
a
formed in a substrate
102
, copper atoms emitted from the target travel straight and are deposited in a concentrated manner at the inlet portion of the recess
102
a,
thus forming the overhang portion (projecting portion) A. If the overhang portion A is formed at the inlet portion of the recess
102
a,
then the inlet portion of the recess
102
a
is blockaded by copper
104
before copper atoms are sufficiently deposited in the interior of the recess
102
a.
Therefore, after this blockade occurs, it prevents copper from being filled into the interior of the recess
102
a,
and the coating or filling process cannot help finishing with a void-like defect B left. Thus, it is generally considered that because of presence of the overhang portion A, the minimum size capable of coating or filling copper by the sputter deposition is in the range of 0.13 to 0.15 &mgr;m.
When interconnects are formed by filling copper or copper alloy as a conductive material in the recess by the sputter deposition process, it has heretofore been customary to use metallic materials having a desired crystal grain size, mechanical properties and surface condition by applying a suitable plastic working, heat treatment and machining.
In order to properly machine the target into a desired configuration, as described above, it is necessary to adjust hardness of the metallic materials by suitable heat treatment, particularly, the final annealing.
FIG. 11
shows the relationship between annealing temperature of copper (oxygen free copper A, electrolytic copper B, and phosphorus deoxidized copper C) and Vickers hardness. As is apparent from
FIG. 11
, as the annealing temperature rises, the Vickers hardness decreases drastically, and when the annealing temperature rises from 400° C. to 800° C., the Vickers hardness gradually decreases by about 10. Thus, in order to sufficiently lower the hardness of the target, the annealing should be carried out at a temperature of 600° C. or higher.
FIG. 12
shows the relationship between annealing temperature of pure copper with 5% or less compressive work strain and its crystal grain size obtained at such annealing temperature. As shown in
FIG. 12
, annealing at a temperature of 600° C. makes a fairly great copper grain size of approximately 300 &mgr;m, for example, with lowered hardness. Difference in target grain size is assumed to create varied deposition result. Specifically, it is considered that if the target crystal grain size exceeds the allowable limit, sputtered copper atoms travel in random directions, remarkably impairing perpendicular travel, due to various crystal orientation of the surface of the target. The traveling direction of copper atoms which have been sputtered, i.e., copper atoms emitted from the target due to collision of high-energy particles with the target, varies with the crystal orientation of the target. Therefore, if the target and the substrate are parallelly faced with each other, filling characteristic of copper atoms into the minute recesses formed perpendicularly to the surface of the substrate is greatly impaired, because a number of atoms travel in oblique directions.
FIG. 13
shows the results of filling copper into a minute via formed in a surface of a semiconductor substrate using a copper target of large grains whose diameter is approximately 200 &mgr;m, obtained by annealing thereof at a high temperature described above. As shown in
FIG. 13
, copper
114
is not deposited in the interior of a via
112
having a diameter of approximately 0.15 &mgr;m, formed in the surface of the semiconductor substrate
110
, except for an inlet portion of the via
112
, and the upper part of the via
112
is blockaded while leaving a void
116
. Therefore, it is difficult or impossible to form copper wiring or interconnects having sufficient current capacity. This is presumably caused by oblique traveling characteristic of copper atoms which have been sputtered.
Conventionally, in the semiconductor device having a wiring circuit with a width of 0.13 &mgr;m or less, it has been generally understood that the optimum process consists of formation of the seed layer by sputter deposition, followed by copper electroplating metalization. The primary purpose of the seed layer is that the seed layer serves as an electrolytic cathode for supplying a sufficient amount of current to reduce metal ions in the plating liquid and to precipitate and deposit solid metal on the substrate. This is because as long as the seed layer remains satisfactory, there exists a high possibility of simultaneously realizing three factors; excellent filling property, high conductivity, and electromigration resistance with electroplating. Therefore,
Araki Yuji
Horie Kuniaki
Kato Takao
Ogure Naoaki
Chaudhuri Olik
Ebara Corporation
Smoot Stephen W.
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