High effective area capacitor for high density DRAM circuits usi

Details High effective area capacitor for high density DRAM circuits usi High effective area capacitor for high density DRAM circuits usi

1998-08-17

2000-02-08

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438255, 438656, 438964, H01L 218242

Patent

active

060227753

ABSTRACT:
A method of forming a capacitor for use in DRAM or other circuits is described. A first polysilicon node, which will form the first capacitor plate, is formed on a layer of first oxide on an integrated circuit wafer. A layer of titanium silicide is formed on the first polysilicon node by depositing titanium and reacting the titanium with the polysilicon using a first rapid thermal anneal. The titanium silicide is then agglomerated by means of a second rapid thermal anneal thereby forming titanium silicide agglomerates on the surface of the first polysilicon node with exposed first polysilicon between the titanium silicide agglomerates. The exposed first polysilicon is then etched thereby increasing the surface area of the surface of the first polysilicon node and forming a first capacitor plate. A layer of second oxide is then formed on the first capacitor plate. A patterned layer of second polysilicon is then formed on the layer of second oxide forming a second capacitor plate.

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patent: 5583070 (1996-12-01), Liao et al.
patent: 5930625 (1999-07-01), Lin et al.
patent: 5960280 (1999-09-01), Jeng et al.

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