High dielectric constant materials as gate dielectrics

Details High dielectric constant materials as gate dielectrics High dielectric constant materials as gate dielectrics

2000-10-19

2001-10-02

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S692000, C438S585000, C438S595000

Reexamination Certificate

active

06297107

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing high-density integrated semiconductor devices exhibiting reliable, adherent, high dielectric constant materials for active devices such as MOS transistors formed on a semiconductor substrate. The invention has particular utility in manufacturing high-density integration semiconductor devices, including multi-level devices, with design rules of 0.18 micron and under.
BACKGROUND ART
Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor substrate and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on a semiconductor substrate to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor device. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integration devices employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate oxide and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-channel and n-channel devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
FIG. 1
illustrates a cross-sectional portion of an exemplary CMOS structure comprising a doped semiconductor substrate
10
typically of monocrystalline silicon of a first conductivity type (p or n). The CMOS structure further comprises field oxide area
12
, gate oxide layer
14
, conductive gate electrodes
16
and
18
, typically of polysilicon, formed over gate oxide layer
14
, and stepped source and drain regions
20
and
22
which include lightly or moderately doped shallow extensions
20
A and
22
A. Completing the MOS transistor precursor structure are insulative sidewall spacers
24
A through
24
D, formed on the side surfaces of each of gate electrodes
16
and
18
.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide layers have served as an impetus for the development of newer, high dielectric constant materials as substitutes for conventional silicon oxide-based gate oxide layers. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material's breakdown potential and reliability.
Decreasing the thickness of the gate oxide layer between the gate electrode and the source/drain extension regions together with the relatively high electric field across the gate oxide layer, can undesirably cause charge carriers to tunnel across the gate oxide layer. This renders the transistor “leaky”, degrading its performance. To alleviate this problem, high-k dielectrics (dielectrics that have high dielectric constants) are used as the gate insulator.
It is further desirable that the high dielectric material adheres to the intended adjacent surfaces and has relatively smooth surfaces. Another consideration is that such dielectric materials used should preferably have a high dielectric constant, as compared to the value of 4.1 to 3.9 for a conventionally employed silicon dioxide (SiO
2
) layer.
Hence, it would be highly advantageous to develop a process that would permit the use of optimum materials in the formation of the gate electrode structure. It would also be highly advantageous to develop methodologies capable of optimum MOS transistor formation. Accordingly, there exists a need for a method of manufacturing MOS semiconductor devices with a high dielectric gate dielectric layer that improves device performance.
SUMMARY OF THE INVENTION
An advantage of the present invention is a composite structure having a reliable, high dielectric layer between a gate electrode and a semiconductive substrate and methods of their formation.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming a composite structure comprising a semiconductor substrate, a high dielectric layer on the semiconductor substrate and a gate electrode on the high dielectric layer. The method comprises: forming a sacrificial gate oxide layer on a surface of a semiconductor substrate; forming a sacrificial gate electrode on the sacrificial gate oxide layer, depositing an insulating layer over the substrate and adjacent to the sacrificial gate electrode; removing the sacrificial gate electrode; removing the sacrificial gate oxide layer to expose the surface of the substrate; applying a metalorganic compound on the surface of the substrate; and forming a metal oxide layer on the surface of the substrate from the applied metalorganic compound. Advantageously, forming the metal oxide layer provides a gate dielectric having a high dielectric constant thereby improving the quality and reliability of a device fabricated from the semiconductor structure.
Embodiment of the present invention include forming the metal oxide layer by spin coating a solution containing the metalorganic compound, such as a solution containing a metal alkoxide, metal b-diketonate, metal dialkylamide, metal carboxylate, and then pyrolizing the applied metalorganic compound in an oxidizing ambience at a temperature of about 300° C. to about 900° C.
Another aspect of the present invention includes a method of forming a semiconductor device having a metal oxide layer as the gate dielectric layer. The method comprises: forming a sacrificial gate oxide layer on a semiconductor substrate; forming a first gate electrode on the sacrificial gate oxide layer; depositing an insulating on the substrate and adjacent to the first gate electrode; removing the first gate electrode; removing the sacrificial gate oxide layer to expose the substrate thereunder; forming a metal oxide layer on the exposed surface of the semiconductor substrate; and forming a second gate electrode on the metal oxide layer. Advantageously, the metal oxide layer can be formed to a thickness of about 50 Å to about 10 Å by solution chemical deposition followed by pyrolysis.
Another aspect of the present invention is a MOS device having a high dielectric gate oxide. The device comprises: a semiconductor substrate having a surface; a pair of spaced apart source and drain regions formed in the substrate and extending from the surface to a depth below the surface; a thin metal oxide layer formed on the surface of the substrate and between the source and drain regions; a gate electrode formed over and in contact with the metal oxide layer having insulative sidewall spacers formed on opposite side surfaces thereof, a dielectric layer adjacent to the insulative sidewall spacers and over the substrate. A

Affiliated with

Also associated with

Rating

High dielectric constant materials as gate dielectrics does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High dielectric constant materials as gate dielectrics, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High dielectric constant materials as gate dielectrics will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2556876